| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Signal converter | JP692783 | 1983-01-18 | JPS59132229A | 1984-07-30 | IZUMI YOSHIHIRO |
| PURPOSE:To attain the selection of A/D and D/A conversion by providing a conversion mode switching means and an analog lead-out means to a D/A converting circuit being a component of an A/D converting circuit. CONSTITUTION:The conversion mode switching means 8 and the lead-out means 6, 7 extracting an analog output signal are added to the A/D converting circuit functioning the D/A converting circuit 5 as a component. In operating this signal converter as the D/A converting circuit 5, a signal is converted to an analog signal and extracted from the terminal 7 by controlling a control logic circuit 3 by the conversion mode switching means 8, releasing the closed loop and giving a digital input signal to be converted to an output terminal 4. | ||||||
| 182 | Data converter | JP10593082 | 1982-06-18 | JPS58222615A | 1983-12-24 | YAMAGUCHI KAZUFUMI; NAKAGAWA ATSUSHI; YAMASHITA ICHIROU |
| PURPOSE:To speed up the titled converter, by providing two systems of output terminals as analog current output terminals of a D/A converter in providing A/D, D/A mode switching function, for switching the modes without using an analog switch. CONSTITUTION:The D/A converter 19 has two output terminals 17, 18 with no mutual interference. Further, when a mode selecting terminal is ''L'', a serial digital signal inputted from a digital input terminal 24 is inputted to a successive comparison register 21, converted into a parallel data, inputted to the D/A converter 19, outputted to an analog output terminal 26 from an output terminal 17 via an operational amplifier 25, and the D/A conversion is done. When the state of a terminal 23 is ''H'' inversely, a switch 22 passes a signal comparing a voltage depending on a current flowing from an analog input terminal 27 to the output terminal of the D/A converter 19 and a ground potential, through a successive comparison register, the signal is converted successively and outputted to a parallel digital output terminal 30 for the A/D conversion. | ||||||
| 183 | Pcmsignal-to-analog signal converter | JP5839482 | 1982-04-09 | JPS57193121A | 1982-11-27 | MIRUMIRA RAMARAO DEWARAKANASU |
| 184 | Two-way code converting system | JP1547681 | 1981-02-04 | JPS57129525A | 1982-08-11 | KARIBE HIROHISA; IKEZAWA MASUSHI; MATSUMURA TOSHIHIKO; FUKUI HIROKAZU |
| PURPOSE:To realize the asynchronous action of two-way code conversion, by providing the 1st PLL circuit plus its subordinate 2nd PLL circuit. CONSTITUTION:The 2nd PLL circuit 25 receives clocks CLK1 and CLK2 of different phases which have a comparatively high frequency compared with the clock that is produced from a voltage control type oscillator within the 1st PLL circuit 24. Then one of these two clocks is selected through a clock selecting circuit 31 to be used as a clock CLK3. This clock CLK3 is divided by a frequency divider circuit 32 to produce a clock corresponding to a receiving synchronous signal 27, and the phase comparison is carried out through a phase comparator 30. The clock is consecutively used if the state of phase is satisfactory and then replaced with another clock if the state of phase becomes unsatisfactory. | ||||||
| 185 | JPS57501056A - | JP50187080 | 1980-12-22 | JPS57501056A | 1982-06-10 | |
| 186 | Two-way code converter | JP16251280 | 1980-11-18 | JPS5787236A | 1982-05-31 | KARIBE HIROHISA; MATSUMURA TOSHIHIKO |
| PURPOSE:To reduce the circuit scale, by determining polarity inversion by a sign bit of an input digital signal and information used for a DA converter, in the two-way code converter for AD conversion and DA conversion. CONSTITUTION:An input analogue signal Ain is applied to positive and negative unipolar DACs 11 and 12, and switches 17-22 perform such switching control that the positive unipolar DAC 11 is used as a local decoder for AD conversion when the input analogue signal Ain has a positive polarity and the negative unipolar DAC 12 is used as a local decoder for AD conversion when the input an analogue signal Ain has a negative polarity. The unipolar DAC which is not used as the local decoder in this case is used for DA conversion, and it is determined whether the polarity should be inverted or not in a polarity inverting circuit 14 in the basis of the sign bit of an input digital signal Din and information indicating which DAC of positive and negative unipolar DACs 11 and 12 is used for DA conversion. Consequently, even if unipolar DACs are used, resampling after polarity discrimination is unnecessary, and the holding circuit is omitted. | ||||||
| 187 | Two-way code converter | JP16251180 | 1980-11-18 | JPS5787235A | 1982-05-31 | KARIBE HIROHISA; MATSUMURA TOSHIHIKO |
| PURPOSE:To facilitate making the two-way code converter for AD conversion and DA conversion into an integrated circuit, by using one reference power source and by using a part of the circuit for AD conversion and DA conversion in common. CONSTITUTION:Unipolar DACs 11 and 12 are provided which hold an input signal temporarily, and one unipolar DAC12 is used as a local demodulator for AD conversion, and the other unipolar DAC11 is switched to be used for holding an input signal during the polarity discrimination time for AD conversion and to be used as a DA converter for DA conversion. Thus, only one reference power source Vr is required, and the holding circuit is omitted, and therefore, the circuit scale is reduced to facilitate making this converter into an integrated circuit. | ||||||
| 188 | Data converter | JP7512380 | 1980-06-03 | JPS56169933A | 1981-12-26 | YAMAGUCHI KAZUFUMI; HORIO YASUHIKO |
| PURPOSE:To enable two functions of A/D and D/A converters, by switching an output of a sequential comparison register and an input to be D/A-converted. CONSTITUTION:Between an output line of a sequential comparison register 30 and a D/A converter 10, a plurality of switch circuits 5-7 which can be switched by an operating selection signal are provided. At the A/D converting operation, the sequential comparison register 30 is connected to the D/A converter 10, D/A converting operation switch circuits 5-7 are switched to opposite side, the input of the D/A converter 10 is connected only to a digital output terminal 8, and the digital output terminal 8 is usable as the input pins for D/A conversion. An operational amplifier 9 is required for D/A converting operation only and it is connected with external pins. | ||||||
| 189 | Analog-to-digital and digital-to-analog converter circuit | JP6615480 | 1980-05-19 | JPS56162534A | 1981-12-14 | NAKASHIMA MASAHIKO |
| PURPOSE:To incorporate a D/A converter easily when integrating a parallel A/D converter by generating a group of reference voltages for A/D and D/A conversion by using a resistance circuit in common. CONSTITUTION:A group of reference voltages is generated by dividing a refererence voltage applied to a reference voltage input terminal 3 by a resistance circuit 4, and then compared with an input analog voltage applied to an analog input terminal 1 by comparators 5 provided corresponding to respective reference voltages. In this case, each comparator generates a ''1'' or ''0'' output depending upon whether the input analog voltage is higher than the reference voltate. Further, a digital input signal having a prescribed code is inputted to a decoder 14, which decomposes a digital code consisting of three bits, for example, into eight control signals; in this case, only one of them is held at ''1'', and others at ''0'' corresponding to the input signals and the circuit 4 performs D/A conversion through an analog multiplexer 15. | ||||||
| 190 | Signal converter circuit | JP15660576 | 1976-12-27 | JPS5381060A | 1978-07-18 | TAKEGAWA TOUJIROU |
| PURPOSE: To convert signals at high precision by transferring charges among capacitance elments by means of field effect transistor IGFEY if the insulating gate type. COPYRIGHT: (C)1978,JPO&Japio | ||||||
| 191 | Pcm encoder*decoder | JP5651577 | 1977-05-18 | JPS52141161A | 1977-11-25 | JAMES EDWIN DALLEY |
| 192 | JPS5039037A - | JP7217074 | 1974-06-24 | JPS5039037A | 1975-04-10 | |
| 193 | Integrated circuit | JP2002077053 | 2002-03-19 | JP3910868B2 | 2007-04-25 | 芳徳 吉川; 昌史 大久保; 篤 日高; 篤 松田; 徹 水谷; 賢一 美濃部; 広美 難波 |
| 194 | Signal conditioning circuit and method comprises a Adc / dac complex sensor system | JP53929999 | 1998-12-18 | JP2001523429A | 2001-11-20 | ザーノッキ，ウォルター; ホルンベック，ニール・ダブリュ; ルーガー，ティモシー; ロックナー，ウィリアム |
| (57)【要約】 電子的に較正されるセンサ１００は、信号調整回路１０４に結合される出力を有する検知素子１０２を備える。 信号調整回路１０４は、検知素子出力上の温度および部分間変動を補償するように演算効率が高く動作可能であり、利用可能なセンサ出力信号を提供する。 信号調整回路１０４は、アナログ−デジタル／デジタル−アナログ（ADC/DAC）変換装置１１２を備える。 ADC/DAC１１２は、アナログ入力信号のアナログ−デジタル変換とデジタル出力信号のデジタル−アナログ変換の両方を実行することができる。 ADC/DAC１１２は、さらに、アナログ信号を入力信号調整回路１０４，１０６に提供する。 | ||||||
| 195 | Codec | JP4489492 | 1992-03-02 | JP2809541B2 | 1998-10-08 | OKAMOTO SEIJI |
| 196 | Connected analog-digital and digital-analog conversion system | JP8771797 | 1997-03-20 | JPH09258902A | 1997-10-03 | JIYONA FUCHIRI; MARUSERO REONE; ANNAMARIA ROTSUSHI |
| PROBLEM TO BE SOLVED: To selectively use a system as a digital-analog converter and an analog-digital converter by tuning a digital multiplexer to the sampling and update clock signals of a continuous approximate register and permitting the digital multiplexer to select input data or a digital value. SOLUTION: The continuous approximate register 33 decides the constitution of a network on the internal digital-analog converter 31, compares an analog value outputted from the digital-analog converter 31 with A/D input data and D/A feedback by a comparator 32 and executes update with the compared result. The update clock signal, the sampling of the continuous approximate register 33 and the digital multiplexer MUX1 34 are tuned and the digital multiplexer MUX1 34 selects a digital word contained in the continuous approximate register 33 or D/A input data. COPYRIGHT: (C)1997,JPO | ||||||
| 197 | Conversion device | JP24470988 | 1988-09-30 | JP2527793B2 | 1996-08-28 | クリスチヤン・ジヤガール; ミツシエル・フエリイ |
| 198 | Analog-to-digital converter | JP3590784 | 1984-02-29 | JPH0628339B2 | 1994-04-13 | NUNOKAWA HIDEO; YAMAGUCHI SATORU; TAKAHASHI HITOSHI |
| 199 | Analog signal processing unit | JP12908385 | 1985-06-13 | JPH0614615B2 | 1994-02-23 | BURUUSU JEI PENII |
| 200 | JPH0262969B2 - | JP50176782 | 1982-04-21 | JPH0262969B2 | 1990-12-27 | OORUGUTSUDO ROBAATO NOOBURU; KERII SUTEIIBUN HAARO |
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