| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | ANALOG READOUT PREPROCESSING CIRCUIT FOR CMOS IMAGE SENSOR AND CONTROL METHOD THEREOF | US15538514 | 2014-12-29 | US20170353685A1 | 2017-12-07 | Liyuan Liu; Nanjian Wu; Zhiqiang Guo |
| The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals. | ||||||
| 62 | Converting circuit with control circuit to detect signals input into the converting circuit, and communication device | US14462961 | 2014-08-19 | US09276601B2 | 2016-03-01 | Jiangang Wu; Haifeng Shen; Jiaqing Wang |
| A converting circuit and a communication device are provided. The converting circuit includes: a sample hold circuit for receiving an analog signal; a Digital to Analog Converter (DAC); a comparator being connected with an output end of the sample hold circuit and an output end of the DAC; and a control circuit being connected with an output end of the comparator, wherein when the sample hold circuit receives an analog signal, the control circuit controls the sample hold circuit and the comparator to work, controls an output of the DAC based on an output of the comparator, and outputs a corresponding digital signal; and when the control circuit detects a digital signal is input, the control circuit controls the DAC to convert the digital signal into an corresponding analog signal and output the corresponding analog signal. The converting circuit can reduce chip area and chip cost. | ||||||
| 63 | CONVERTING CIRCUIT AND COMMUNICATION DEVICE | US14462961 | 2014-08-19 | US20150145708A1 | 2015-05-28 | Jiangang WU; Haifeng SHEN; Jiaqing WANG |
| A converting circuit and a communication device are provided. The converting circuit includes: a sample hold circuit for receiving an analog signal; a Digital to Analog Converter (DAC); a comparator being connected with an output end of the sample hold circuit and an output end of the DAC; and a control circuit being connected with an output end of the comparator, wherein when the sample hold circuit receives an analog signal, the control circuit controls the sample hold circuit and the comparator to work, controls an output of the DAC based on an output of the comparator, and outputs a corresponding digital signal; and when the control circuit detects a digital signal is input, the control circuit controls the DAC to convert the digital signal into an corresponding analog signal and output the corresponding analog signal. The converting circuit can reduce chip area and chip cost. | ||||||
| 64 | System including feedback circuit with digital chopping circuit | US13527120 | 2012-06-19 | US08917195B2 | 2014-12-23 | Mario Motz; Udo Ausserlechner |
| A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The digital to analog converter circuit is configured to convert an error signal into an analog signal that is received by the second circuit to reduce ripple error. | ||||||
| 65 | Data-driven noise reduction technique for Analog to Digital Converters | US14163560 | 2014-01-24 | US20140210653A1 | 2014-07-31 | Pieter Joost Adriaan Harpe |
| A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τMV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τMV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output. | ||||||
| 66 | FIELDBUS ADAPTER AND METHOD OF USING FIELDBUS ADAPTER | US13556371 | 2012-07-24 | US20130027237A1 | 2013-01-31 | Mitsuhiro WASHIRO |
| A fieldbus adaptor connected between a fieldbus that handles a digital signal and a field device that handles an analog signal, the fieldbus adaptor comprising a first connection unit detachably connected to the fieldbus, a second connection unit detachably connected to the field device, and a conversion unit provided between the first connection unit and the second connection unit, the conversion unit bidirectionally converting the digital signal handled by the fieldbus and the analog signal handled by the field device. | ||||||
| 67 | SYSTEM INCLUDING FEEDBACK CIRCUIT WITH DIGITAL CHOPPING CIRCUIT | US12717294 | 2010-03-04 | US20110215955A1 | 2011-09-08 | Mario Motz; Udo Ausserlechner |
| A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The chopping circuit is configured to receive the digital output signals and provide error signals that represent ripple error in the digital output signals. The integrator circuit is configured to accumulate the error signals and provide an accumulated error signal. The digital to analog converter circuit is configured to convert the accumulated error signal into an analog signal that is received by the second circuit to reduce the ripple error. | ||||||
| 68 | DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC | US12345844 | 2008-12-30 | US20100164761A1 | 2010-07-01 | Ho Ming Karen Wan; Yat To William Wong; Kwai Chi Chan; Hok Mo Yau; Tin Ho Andy Wu; Kwok Kuen David Kwong |
| A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes. | ||||||
| 69 | Combined AD/DA Converting Apparatus | US11766687 | 2007-06-21 | US20070296622A1 | 2007-12-27 | Yasumasa Hayakawa; Akira Yoshida; Taichiro Kawai |
| A combined AD/DA converting apparatus carrying out AD conversion of an analog input signal to output a converted digital signal or carrying out DA conversion of a digital input signal to output a converted analog signal based on a conversion selection signal for selecting AD conversion or DA conversion comprises an input signal selection circuit configured to select one analog signal out of a plurality of analog input signals to be output based on an input selection signal; an input sample hold circuit configured to sample and hold the analog input signal output from the input signal selection circuit; a DA converter configured to convert a digital signal into an analog signal to be output; a comparator circuit configured to output a comparison signal that indicates a size relation between the analog input signal output from the input sample hold circuit and the analog signal output from the DA converter; a sequential comparison register configured to define sequentially each place of a digital signal stored in the register based on the comparison signal output from the comparison circuit; a selection circuit configured to receive the digital signal stored in the sequential comparison register, the digital input signal, and the conversion selection signal, the selection circuit being configured to output the digital signal stored in the sequential comparison register to the DA converter when the conversion selection signal indicates AD conversion, and to output the digital input signal to the DA converter when the conversion selection signal indicates DA conversion; and a controlling unit configured to output the input selection signal when the conversion selection signal indicates DA conversion. | ||||||
| 70 | Digital-analog-conversion circuit having function of automatic offset adjustment | US10367966 | 2003-02-19 | US06819273B2 | 2004-11-16 | Tohru Mizutani; Hiromi Nanba; Atsushi Matsuda; Atsushi Hitaka; Masashi Okubo; Yoshinori Yoshikawa; Kenichi Minobe |
| An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal. | ||||||
| 71 | Reference voltage circuit | US10246342 | 2002-09-18 | US06686798B2 | 2004-02-03 | Richard Gaggl |
| Reference voltage circuit for generating at least one constant reference voltage (Vref) with a first current mirror circuit (54), which is connected to a positive supply voltage (Vdd) and mirrors a reference current (Iref) with a first current mirror factor (N1) to form a first mirrored reference current (IS1); a second current mirror circuit (67), which is connected to a negative supply voltage (Vss) and mirrors a reference current (Iref) with a second current mirror factor (N2) to form a second mirrored reference current (IS2); a resistor string (71), which comprises a plurality of resistors (71-i) connected in series and is wired between the two current mirror circuits (54, 67); one end (42) of the resistor string (71) being supplied with the first mirrored reference current (IS1) from the first current mirror circuit (54) and the other end (73) of the resistor string (71) delivering the second mirrored reference current (IS2) to the second current mirror circuit (67), the two current mirror factors (N1, N2) of the current mirror circuits (54, 67) being equal, so that constant reference voltages can be picked off at the resistors (71-i) of the resistor string (71). | ||||||
| 72 | Offset calibration system | US10156365 | 2002-05-28 | US06624772B1 | 2003-09-23 | Jeffrey C. Gealow; Thomas J. Barber, Jr.; Paul F. Ferguson, Jr.; Xavier S. Haurie |
| An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit. | ||||||
| 73 | Reference voltage circuit | US10246342 | 2002-09-18 | US20030067346A1 | 2003-04-10 | Richard Gaggl |
| Reference voltage circuit for generating at least one constant reference voltage (Vref) with a first current mirror circuit (54), which is connected to a positive supply voltage (Vdd) and mirrors a reference current (Iref) with a first current mirror factor (N1) to form a first mirrored reference current (IS1); a second current mirror circuit (67), which is connected to a negative supply voltage (Vss) and mirrors a reference current (Iref) with a second current mirror factor (N2) to form a second mirrored reference current (IS2); a resistor string (71), which comprises a plurality of resistors (71-i) connected in series and is wired between the two current mirror circuits (54, 67); one end (42) of the resistor string (71) being supplied with the first mirrored reference current (IS1) from the first current mirror circuit (54) and the other end (73) of the resistor string (71) delivering the second mirrored reference current (IS2) to the second current mirror circuit (67), the two current mirror factors (N1, N2) of the current mirror circuits (54, 67) being equal, so that constant reference voltages can be picked off at the resistors (71-i) of the resistor string (71). | ||||||
| 74 | Integrated circuit for conditioning and conversion of bi-directional discrete and analog signals | US09694881 | 2000-10-24 | US06448914B1 | 2002-09-10 | Mohamed Younis; James W. Ernst |
| An integrated circuit chip for interfacing a digital computer to sensors and controlled devices can be configured to accept and provide a variety of analog and discrete input and output signals. The circuit includes a plurality of signal conditioning cells, a plurality of signal conversion cells, and input and output signal multiplexors. | ||||||
| 75 | Analog-to-digital conversion | US38887 | 1998-03-11 | US06087970A | 2000-07-11 | Roger Panicacci |
| A circuit has an analog-to-digital converter that, during a first mode of the circuit, is configured to use capacitors of the converter to furnish a digital representation of an analog input voltage. The circuit also has an amplifier that has a gain responsive to a capacitance, and the switches are configured to, during a second mode of the circuit, selectively connect the capacitors to the amplifier to select the gain. | ||||||
| 76 | Signal conditioning circuit including a combined ADC/DAC, sensor system, and method therefor | US17617 | 1998-02-02 | US5995033A | 1999-11-30 | William Roeckner; Neal Hollenbeck; Timothy Rueger; Walter Czarnocki |
| An electronically calibrated sensor (100) includes a sensing element (102) with an output coupled to a signal conditioning circuit (104). The signal conditioning circuit (104) is adapted to be highly computationally efficient and operable for compensating for temperature and part-to-part variation on the sensing element output for providing a useable sensor output signal. The signal conditioning circuit (104) includes an analog-to-digital/digital-to-analog (ADC/DAC) conversion device (112). The ADC/DAC (112) is operable to perform both analog input signal analog-to-digital conversion and digital output signal digital-to-analog conversion. The ADC/DAC (112) is further adapted to provide analog control signals to input signal conditioning circuits (104, 106). | ||||||
| 77 | Self-calibrating reversible pipeline analog to digital and digital to analog converter | US841100 | 1997-04-29 | US5929796A | 1999-07-27 | Ion E. Opris; Laurence Douglas Lewicki; Lee Stoian |
| A self-calibrating reversible pipeline analog to digital converting architecture configured to convert an input analog signal to an output digital signal and further to convert an input digital signal to an output analog signal is disclosed. The reversible pipeline architecture self-calibrates to compensate for adverse effects upon the linearity during signal conversion using a digital correction procedure. The same digital correction coefficients are used during both analog to digital conversion as well as during digital to analog conversion. The self-calibrating reversible converting architecture includes a reduced gain stage to create the necessary redundancy for the digital correction. Furthermore, the self-calibrating reversible converting architecture includes an overflow reduction stage to generate redundancy for the digital correction. | ||||||
| 78 | Edge triggered sample and hold circuit and circuits constructed from same | US410227 | 1995-03-24 | US5608402A | 1997-03-04 | Robert J. Distinti |
| An Operational Analog to Digital (SYMAD) Convertor cell for converting an analog signal into a discrete binary code. An analog signal is processed by sample and hold circuitry and then compared to a reference voltage by a comparator. The comparator output is the converted digital output. This output is coupled back to the control input of an analog switch which selects either the reference voltage or a predetermined potential, typically zero volts, to couple to an inverting input of an operational amplifier. The analog signal input is also coupled to the non-inverting input of the operational amplifier. The operational amplifier is configured as a differential amplifier with a gain of two. If the digital output of the comparator is a logic 1, then the operational amplifier output is two times the difference between the analog signal and the reference voltage. If the digital output of the comparator is a logic 0, then the output of the operational amplifier is two times the analog signal. As many SYMAD cells as necessary may be provided to obtain a desired resolution. | ||||||
| 79 | Analog-to-digital converter | US316255 | 1994-09-30 | US5594438A | 1997-01-14 | Spyros Panaoussis |
| An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1."When the modified signal is larger than or equal to the stated sum, the converter stage outputs a binary "1", and when the modified signal is smaller than the sum, a binary "0" is output. In digital-to-analog mode, binary inputs to each stage determine the reference signals to be summed in order to produce an analog output. The restoring filter may be used to restore the original incoming analog signal, including its sign. | ||||||
| 80 | Signal converting apparatus utilizing an analog-digital converting section and a digital-analog converting section | US240218 | 1994-05-09 | US5404141A | 1995-04-04 | Eiji Ohara |
| There is provided a signal converting apparatus using a semiflash type A/D converter comprising an analog-digital (A/D) converting section and a digital-analog (D/A) converting section, wherein the apparatus has an input switching circuit for switching in a manner such that an input of the D/A converting section is set to a conversion output of the A/D converting section during the A/D converting operation and the input of the D/A converting section is set to an external input during the D/A converting operation. | ||||||
QQ群二维码
意见反馈
意见反馈