| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | Ad and da converting circuit with monitoring function for state of quantization by ad conversion | JP18227782 | 1982-10-18 | JPS5972221A | 1984-04-24 | MORIYAMA MASARU |
| PURPOSE:To easily monitor the state of quantization by A/D conversion through simple constitution by using the A/D converter of a sequential comparison type A/D converting circuit as a D/A converting circuit through a switching circuit. CONSTITUTION:The movable contact (v) of a changeover switch SW1 is connected to the output terminal (c) of a D/A converter DAC used as a component of an A/D and D/A converting circuit A-D-A. On the other hand, a changeover switch SW2 is provided between the output side of a sequential comparison type register SAR and the input terminal of the DA converter DAC. Then, the switch SW1 is connected to a summing point (a) and the switch SW2 is turned on to operate the circuit A-D-A as an A/D converter; while the switch SW1 is connected to the side of an analog signal output circuit POC, the switch SW2 is turned off to operate the circuit A-D-A as a D/A converter. | ||||||
| 162 | Digital and analog two-way converter | JP17991481 | 1981-11-09 | JPS5880926A | 1983-05-16 | AZEGAMI TADASHI |
| PURPOSE:To perform both analog-to-digital conversion and digital-to-analog conversion by providing a D/A conversion part and comparator, a digital signal generation part and one-way control gate, and a two-way control gate. CONSTITUTION:The conversion analog output of a D/A conversion part 1 is compared with an input analog signal from a terminal 4 by a comparator 3, whose comparison output is used to control a digital signal generation part 5. Its digital output is supplied to the input side of a D/A conversion part 1 through a one-way control gate 15. The digital input of the D/A conversion part 1 is coupled to a digital signal external terminal 17 through a two-way control gate 16. Then when the gate 15 is opened, an input analog signal is converted into a digital signal, which is outputted to the external terminal 17 through the gate 16, thus obtaining the function of an A/D converter. On the other hand, the gate 15 is closed to supply a digital signal from the external terminal 17 to the D/A conversion part 1, obtaining the function of a D/A converter. | ||||||
| 163 | JPS58500684A - | JP50172582 | 1982-04-21 | JPS58500684A | 1983-04-28 | KELLEY STEPHEN HARLOW; ULMER RICHARD WALTER |
| 164 | Converting circuit | JP5583481 | 1981-04-14 | JPS57170626A | 1982-10-20 | NAKAMURA TETSUYA; YASUURA NOBUSHI; SHIOZAKI MAKOTO; OGISO HARUHIKO; SAKA MITSUHIRO; ISHII MIYA |
| PURPOSE:To use parts, which are used for an A/D and a D/A converter, in common and to decrease the number of the parts by using an I/O port, a buffer and a resistance ladder for the D/A converter when they are not used for the A/D converter. CONSTITUTION:This converting circuit normally operates as a D/A converter. In this case, the port 111 of an I/O port 11 has a level LOW, an analog switch 24a is cut off, and an analog switch 24b is closed. Therefore, digital data outputted from the port 11 is passed through a buffer 12 and a resistance ladder to be converted into analog data, which is outputted to a terminal 131 and then applid to an integrating circuit 26 as a sample holding circuit through the switch, so that it is outputted to an analog data output terminal 271 through a voltage follower circuit 27. When a computer requires the analog data, the port 11 is held at a high level to turn the switch 24a on and to turn the switch 24b off. Consequently, the converting circuit operates as an A/D converter. | ||||||
| 165 | JPS57501057A - | JP50193781 | 1980-12-22 | JPS57501057A | 1982-06-10 | |
| 166 | Method of adjusting zero point of analog value comparator | JP12826681 | 1981-08-18 | JPS5761332A | 1982-04-13 | ROOBERUTO REHINAA; FURICHIYOFU FUON JITSUHIYARUTO; PEETAA PIKARUTO |
| 167 | JPS5327141B2 - | JP7217074 | 1974-06-24 | JPS5327141B2 | 1978-08-07 | |
| 168 | Method and circuit for converting analog signal to digital signal and vice versa | JP9120576 | 1976-07-30 | JPS5216962A | 1977-02-08 | ERUNSUTO HEEFUAA; PEETAA HIRUSHIYUMAN; KURAUSU BUINTSUAA |
| 169 | Anaroguudeijitaruoyobi deijitaruuanaroguhenkanniokeru kairyo | JP5019475 | 1975-04-24 | JPS5115963A | 1976-02-07 | JON UIRIAMU ARUDAMU; TAARANSU KOTSUKAARIRU |
| 170 | JPS50113162A - | JP12451074 | 1974-10-30 | JPS50113162A | 1975-09-05 | |
| 171 | Field bus adapter and method of using the same | JP2011165408 | 2011-07-28 | JP2013029978A | 2013-02-07 | WASHIRO MITSUHIRO |
| PROBLEM TO BE SOLVED: To provide a field bus adapter which can take an analog system field device in a self-supporting type control system.SOLUTION: A first connection unit is detachable from a field bus. A second connection unit is detachable from a field device. Conversion means is disposed between the first connection unit and the second connection unit, and a digital signal treated in the field bus and an analog signal treated in the field device are bi-directionally converted. | ||||||
| 172 | Ad / da conversion compatible apparatus | JP2006171793 | 2006-06-21 | JP4839139B2 | 2011-12-21 | 昭 吉田; 泰正 早川; 多一郎 河合 |
| 173 | Ad/da conversion combined apparatus | JP2006171793 | 2006-06-21 | JP2008005159A | 2008-01-10 | HAYAKAWA YASUMASA; YOSHIDA AKIRA; KAWAI TAICHIRO |
| PROBLEM TO BE SOLVED: To shorten processing time in an AD/DA conversion combined apparatus. SOLUTION: The apparatus is provided with an input signal selection circuit which selects and outputs an analog signal from among a plurality of analog input signals; an input sample hold circuit which carries on sampling and holds; a D/A converter which converts a digital signal to an analog signal and outputs; a comparison circuit which outputs a comparison signal which shows the magnitude relation of the input analog signal from the input sample-and-hold circuit and the analog signal from the D/A converter; a successive comparison register which successively decides on each digit of the digital signal, based on the output comparison signal; a selection circuit which receives a stored digital signal, a digital input signal, and a conversion selective signal, outputs the digital signal to be stored in the successive comparison register, to the D/A converter in a case of A/D conversion, and outputs the digital input signal to the D/A converter, in the case of D/A conversion; and a control unit which outputs the input selective signal, in the case that the conversion selection signal indicates D/A conversion. COPYRIGHT: (C)2008,JPO&INPIT | ||||||
| 174 | Integrated circuit for converting Shi conditioned bi-directional discrete and analog signal and | JP2002547088 | 2001-10-24 | JP2004515013A | 2004-05-20 | アーンスト，ジェイムズ・ダブリュー; ユーニス，モハメド |
| ディジタル・コンピュータ（１０３）をセンサ（１０１）及び被制御型装置（１０７）にインターフェースするための集積回路チップ（１０５）は、様々な離散的及びアナログの入力及び出力信号を受け入れ且つ与えるよう構成され得る。 当該回路は、複数の信号条件付けセル（１１１）、複数の信号変換セル（１１３）、及び入力及び出力信号マルチプレクサを含む。
【選択図】図１ |
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| 175 | Analog device calibration method, analog integrated circuit and codec | JP29928795 | 1995-10-25 | JPH08279720A | 1996-10-22 | DAGURASU JIYOOJI MAASHIYU; ROBAATO HENRII BUAIDEN |
| PROBLEM TO BE SOLVED: To decide an effective gain required to calibrate each path not trimmed by comparing an output signal generated in the path not trimmed with a signal in a trimmed path. SOLUTION: A programmable CODEC 100 of 16 channels, for example, requires highly precise trimming for only one direction of channels of T75358 channel A/D-D/A converters 104/106. Then the trimmed path is used for a reference by a DSP as a reference to calibrate other 15 channel paths included in the converters. Then the DSP 102 applies a known voltage signal to generate an output signal to the respective paths and the output signal produced from the path not trimmed is compared with the signal generated by the trimmed path. Then the effective gain is decided to calibrate the path not trimmed. COPYRIGHT: (C)1996,JPO | ||||||
| 176 | Method of controlling charge of storage battery for electricrailcar | JP17467484 | 1984-08-21 | JPS6152116A | 1986-03-14 | TANAKA AKIFUMI |
| 177 | JPS612333B2 - | JP6615480 | 1980-05-19 | JPS612333B2 | 1986-01-24 | NAKAJIMA MASAHIKO |
| 178 | A/d converter | JP10165985 | 1985-05-15 | JPS60260229A | 1985-12-23 | MARUCHIN MASHIEKU; GEORUGU MASHIYUTONAA |
| 179 | Analog-digital converter | JP3590784 | 1984-02-29 | JPS60182220A | 1985-09-17 | NUNOKAWA HIDEO; YAMAGUCHI SATORU; TAKAHASHI HITOSHI |
| PURPOSE:To attain A/D conversion for an analog signal and also A/D conversion for a digital signal by providing a setting device setting a prescribed value to a D/A converter of a sequential conversion form A/D converter. CONSTITUTION:In using the titled converter as an A/D converter, a switch 11 is set to the position shown in solid lines. Since a timing signal phiA is applied to a gate of a transistor (TR)3 of a comparator 5' and a timing signal phiB is applied to a gate of a TR4, an input signal is subjected to A/D conversion. In using the converter as a D/A converter next, a digital value corresponding to an analog output outputted is set to a setting device 12. The set value is fed to the A/D converter 7 via a resistor 6, and the corresponding analog output is outputted from the converter 7. On the other hand, a multiplexer 2 selects one of output terminals, e.g., 1'. Then the switch 11 is changed over to the position shown in broken lines. When the signal phiA is fed to the TRs 3, 4 at the same time, the analog output of the converter 7 is outputted to the terminal 1'. | ||||||
| 180 | JPS6016135B2 - | JP9373878 | 1978-08-02 | JPS6016135B2 | 1985-04-24 | |
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