| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 201 | Converter commonly used for analog/digital-digital/ analog conversion | JP2847288 | 1988-02-09 | JPH01202925A | 1989-08-15 | FUJISAWA AKIHIKO |
| PURPOSE: To attain A/D conversion processing and D/A conversion processing by providing a comparator and a latch circuit whose operating mode is switchable by an external signal. CONSTITUTION: An A/D-D/A common use converter is provided, switches 11-0∼11-6 of a switch array are switched by a latch circuit 22 and a timing generating circuit 23, a voltage on a common connection node of capacitor arrays 10-0∼10-6 and a reference voltage are compared by a comparator 20 and a digital output corresponding to the analog input is obtained. Moreover, when the operating mode is switched for the comparator 20 and the latch circuit 22 by using an external signal, the latch circuit 22 latches a digital input and its latch data switches the switch array of each switch by using a latch data. The voltage on the common connection node of the capacitor array is subject to impedance conversion by the comparator 20 and an analog output corresponding to the digital input is transmitted. Thus, the A/D conversion processing and the D/A conversion processing are applied and the chip size is reduced because of the reduction in the number of components. COPYRIGHT: (C)1989,JPO&Japio | ||||||
| 202 | Converter | JP24470988 | 1988-09-30 | JPH01130625A | 1989-05-23 | MITSUSHIERU FUERII; KURISUCHIYAN JIYAGAARU |
| PURPOSE: To easily provide two transmission functions directly opposite to each other by performing an A/D conversion and a D/A conversion by the same constitution element. CONSTITUTION: The output of a digital-analog D/A converter 110 is connected to an attenuator 120 and the output of the attenuator 120 is connected to the input of a comparison mechanism 150 and a sample-and-hold S/H circuit 130. The output of the S/H circuit 130 supplies an analog amount reacting to digital output transmitted through a bus 115 to control logic 140 to a lead wire 185. Also, the output of the comparison mechanism 150 is sent to the control logic 140 and the control logic 140 controls the S/H circuit 160, the D/A converter 110, the attenuator 120 and the S/H circuit 130 and supplies the digital output corresponding to the analog amount inputted to the S/H circuit 160 to the bus 125. Thus, without using the members of high accuracy, the two transmission functions in completely opposite relation are easily realized. COPYRIGHT: (C)1989,JPO | ||||||
| 203 | JPS6151448B2 - | JP10585981 | 1981-07-07 | JPS6151448B2 | 1986-11-08 | TOYOMAKI KAZUYA |
| 204 | A/d and d/a converter | JP5324385 | 1985-03-19 | JPS61212918A | 1986-09-20 | SAKATA TAKESHI; SHIROHIGE NORIYA; UCHISE YOSHIBUMI |
| PURPOSE:To miniaturize the circuit by using one D/A converter, an analog switch and a comparator to apply plural A/D and D/A conversions in parallel. CONSTITUTION:A microcomputer 3 increments a counter by 1 every time one clock is outputted to a D/A converter 4. The microcomputer 3 compares an output value to signal lines Ao1-AoN with a count and gives an analog switch control signal 11 to an analog switch to the coincident signal and the result of the D/A conversion is outputted to the said signal line. Then the microcomputer 3 operates an analog switch control signal 6, the signal of the lines Ai1-AiN is inputted to the comparator 2 and the output is compared with the converter 4. The microcomputer 3 discriminates any of the signals Ai1-AiN depending on the signal 6 and stores the count value to the corresponding data area as the result of A/D conversion. | ||||||
| 205 | JPS612335B2 - | JP14350280 | 1980-10-13 | JPS612335B2 | 1986-01-24 | MORI TOSHIKI; SHIBATA ATSUSHI |
| 206 | JPS612334B2 - | JP6673580 | 1980-05-19 | JPS612334B2 | 1986-01-24 | MORI JUICHI |
| 207 | Analog signal processor | JP12908385 | 1985-06-13 | JPS6112124A | 1986-01-20 | PENNEY BRUCE J |
| 208 | A/d-d/a converter | JP10096484 | 1984-05-18 | JPS60245313A | 1985-12-05 | SUZUKI TOSHIAKI; TANIGAWA YUUJI; MATSUZAKI TOSHIMICHI |
| PURPOSE: To obtain an A/D-D/A converter which has a small LSI chip and also can change a time division utilization ratio by a program, by switching as a time division and using one A/D converter for both A/D conversion and D/A conversion. CONSTITUTION: A D/A converter 27 is provided on an A/D converter for comparing successively an analog input 11 and a value of a D/A converting part 14, which becomes a comparison reference value. This converter is constituted so as to be brought to a switching control by an output pulse of a timing generating part 15 having an A/D enable flag 20 and a D/A enable flag 24, sof that the D/A converting part 14 is switched to an A/D converter and a D/A converter and operated by a multiplexer part 16. In this state, when sending out a signal of the A/D enable flag 20, a D/A output is outputted from an A/D register part 13, and when sending out a signal of the D/A enable flag 24, an analog converting output 17 to an input digital signal of a D/A register part 19 is outputted through the multiplexer part, and also the time sending out the signal of both the flags can be controlled variably. COPYRIGHT: (C)1985,JPO&Japio | ||||||
| 209 | Analog-digital, digital-analog converter | JP24017683 | 1983-12-20 | JPS60130924A | 1985-07-12 | SUZUKI TOSHIAKI |
| PURPOSE:To use the titled converter to both A/D and D/A converting applications in time division by providing a multiplexer section of an output of A/D and D/A and a sample-and-hold section of an output being a D/A converting section to an A/D, D/A converter. CONSTITUTION:The A/D, D/A converter is provided with an A/D register section 13, a D/A register section 19, a multiplexer section 16, a D/A converting section 14, a comparator section 12, a sample holding section 17 and a timing generating section 15 and the D/A converting section used at the A/D conversion is used in common in time division. The operation is divided into two, the A/D conversion is conducted during the period at the first half when the clock pulses are up to eight, and an interruption request signal for the end of A/D conversion is generated at the 9th clock pulse. The bit is decided from the most significant bit (MSB) at each bit by each clock pulse. The D/A conversion is conducted from the 8th clock pulse at the latter half. | ||||||
| 210 | Information signal converter | JP15899783 | 1983-09-01 | JPS6052115A | 1985-03-25 | NODA TSUTOMU; ISO YOSHIMI; KAWABATA KENJI; SATOU TETSUO; MATSUDA TOSHIHIRO |
| PURPOSE:To prevent the increase in the scale of circuit by applying a current from a current source to each of integration circuits selectively and switchingly and applying an output voltage of a prescribed integration circuit to a single voltage comparator circuit. CONSTITUTION:When analog signals AR, AL are applied from analog input terminals 1, 1', capacitors 9, 9' are controlled so that they are discharged alternately via switches 3, 3'. Thus, outputs ER, EL of the amplifiers 6, 6' are compared respectively with reference voltages E1, E2 of voltage comparator circuits 12, 13 and when the voltages ER, EL are respectively equal to the E1, E2, the count of the 1st and 2nd counters (not shown in a figure) of a control circuit 16 is stopped. Then the analog signals AR, AL are digitized alternately via a changeover switch 27 and a digital signal corresponding to an output terminal 2 is extracted in time division multiplex. Similarly, when the digital signal is applied from a digital input terminal 17, an analog signal is outputted from a terminal 26 by using a control circuit 18. | ||||||
| 211 | Analog input/output device | JP9977683 | 1983-06-02 | JPS59223021A | 1984-12-14 | NARIHARA KOUSHIYUU |
| PURPOSE:To offer an analog input/output device which can be operated efficiently and also whose cost is low by using a digital-analog converter for an analog input/output, too, and forming an analog input device and same output device as one body. CONSTITUTION:As for an operation of an analog input, a switch 11 is closed and switch 12 is opened by a controlling circuit 10, and as for an input of a digital- analog converter 4, an output of a comparing register 1 is selected successively by a selector 3, and the output is compared with the analog input by one bit each from the uppermost bit to the lowest bit by a comparator 7. When it is larger than an analog input signal, a digital output corresponding to the analog input is sent out by moving successively the comparing register 1 to the following bit. As for an operation of an analog output, the switch 11 is opened and the switch 12 is closed by the controlling circuit 10, and an output of a register 2 to which a digital input is set is selected by the selector 3, converted to an analog value by the digital-analog converter 4, and outputted to the outside. | ||||||
| 212 | Signal converter | JP8316183 | 1983-05-11 | JPS59207729A | 1984-11-24 | MATSUZAWA AKIRA; INOUE MICHIHIRO |
| PURPOSE:To unify an A/D converter and a D/A converter by a simple constitution by providing a sample hold circuit that uses a D/A conversion output as an input and obtaining an analog conversion output from the circuit during A/D conversion. CONSTITUTION:Pulses (b)-(e) are generated from clock pulse (a) by a logical circuit 13. Input analog signal value ''1'' is held in a sample hold SH circuit 2 by a pulse (b). Utilizing settling lapse time of an analog signal held in the circuit 2, a logical circuit 5 inputs an external input digital value to a D/A conversion section 6, changes a switch 7 to the input side of an SH circuit 8, holds D/A converted 6 analog signal in the circuit 8, and outputs from a terminal 8. Then, the output of the conversion section 6 is connected to a comparator 3 by changing the switch 7 and compared with the analog signal from the circuit 2, converted to a digital signal by the number of pulses (c) in a relational type logical circuit 4 for A/D conversion, and outputted through the circuit 5. Thus, D/A conversion and A/D conversion are made in one period of clock (a). | ||||||
| 213 | Integrating type analog-digital and digital-analog converter | JP17686482 | 1982-10-07 | JPS5966224A | 1984-04-14 | ABE MIKI; SUZUKI TADAO |
| PURPOSE:To simplify the circuit constitution and to attain the cost-down by using in common an analog circuit section comprising a Miller integrating circuit and a current/voltage converting circuit for the A/D and D/A conversion and using also an LPF in common for both purposes. CONSTITUTION:An analog input signal applied to an input terminal 1 is applied to the current/voltage converting circuit 4 via a resistor 2 and an input switch S1. The switch S1 is controlled with a mode switching pulse from a terminal 3, turned on at the A/D converting mode and turned off at the D/A converting mode. The Miller integrating amplifier 6 is constituted by inserting a capacitor 7 in a feedback path of an operational amplifier and a discharge switch S2 is connected in parallel with the capacitor 7. This switch S2 is turned off at all times at the A/D conversion mode. Further, a sampling switch S3 connected to the input of the Miller integrating amplifier 6 samples the input analog voltage at the A/D conversion mode and is connected to ground at all times at the D/A conversion mode. Moreover, the LPF11 is used in common to both conversion modes. | ||||||
| 214 | Digital-analog converting and inverting circuit | JP12872782 | 1982-07-23 | JPS5919429A | 1984-01-31 | CHIBA KAZUHIRO |
| PURPOSE:To eliminate the need for a contact part such as relay and to attain the reliability with a low cost, by performing the on/off-control of a comparator circuit section of an A/D, D/A converters with an external signal. CONSTITUTION:An ON signal is applied to the comparator 17 at the A/D converting mode. An analog A/D converting signal inputted to an input terminal 11 is converted into a current at a V/I converting resistor 13. A signal of a sequential comparator 19 being set in advance passes through a selector 1A and is inputted to a D/A converter 18. This output signal and the V/I converting signal are added and the discrimination of the amplitude is performed by the comparator 17. When larger, 1 is set to the sequential comparator 19 and when smaller, 0 is set thereto. An OFF signal is applied to the comparator 17 at the D/A converting mode. A D/A converting signal applied to an input terminal 1C is selected at a selector 1A to be passes through, and converted by a D/A converter 18 and amplified to a prescribed level and outputted by an amplifier 14. | ||||||
| 215 | Signal converter | JP10657682 | 1982-06-21 | JPS58223921A | 1983-12-26 | ABE MIKI |
| PURPOSE:To attain simple and inexpensive constitution, by attaining a different function with the same circuit constitution on one chip in an integration system. CONSTITUTION:A shift register 60 converting a serial signal into a parallel signal in the 1st mode and converting a parallel signal into a serial signal in the 2nd mode, is arranged, and an input data to a latch circuit 50 is switched suitably so as to obtain the counter output at the 1st mode and the shift register output at the 2nd mode and a counter 40 is constituted to be a binary counter at the 1st mode and a presettable counter at the 2nd mode. As a result, the circuit is made possible in acting like an A-D or a D-A converter under the condition of a suitable mode setting using the same circuit constitution and this method is realized on one chip. | ||||||
| 216 | Encoder and decoder | JP3055182 | 1982-03-01 | JPS58148515A | 1983-09-03 | OKAMOTO SEIJI; MORI SHIGEKAZU; TSUKAGOSHI SHIYOUSAKU; IWATA ATSUSHI |
| PURPOSE:To improve the accuracy of an encoder/decoder, by providing a switch between a switch side terminal of a main and a sub-C ladder and ground, and between the terminal and an output of a buffer amplifier respectively and cancelling an offset voltage stored in the sub-ladder. CONSTITUTION:A companding type decoder is constituted with a condencer ladder, one end of the main C-ladder and the sub-C-ladder of the decoder is connected in common and connected to a non-inverting input of the buffer amplifiers 207, 206. The reset switches 204, 205 are provided between one end of the main and the sub-C-ladder and ground GND, and offset correction switches 208, 209 are provided between terminals of SA1-SA8, SB1-SB4 of the main and the sub-C-ladder and the GND, and between the terminals and the output of the buffer 206 respectively. Further, the DC offset voltage stored in the sub-C-ladder is cancelled automatically, allowing to improve the accuracy of the decoder. | ||||||
| 217 | JPS58500685A - | JP50176782 | 1982-04-21 | JPS58500685A | 1983-04-28 | |
| 218 | Encoding and decoding device | JP10585981 | 1981-07-07 | JPS587918A | 1983-01-17 | TOYOMAKI KAZUYA |
| PURPOSE:To reduce constitutional parts and improve reliability by constituting a titled device so that the constitutional parts can be widely used in common at the operation in both encoding and decoding modes. CONSTITUTION:Since an analog signal compressor AC and an analog signal expander AE are constituted by using common resistors R3-R5 and changeover switches S6, S7 for selecting the quantity of compression and expansion, the number of resistors and alteration switches can be reduced by half in comparison with an ordinary circuit and the number of highly accurate resistors for compression and expansion can be also reduced. Since the device is constituted by a small number of parts, the device is advantageous at the points of cost and spaces and can easily achieve the improvement of reliability of the circuit. | ||||||
| 219 | Code converting device | JP14350280 | 1980-10-13 | JPS5765924A | 1982-04-21 | MORI TOSHIKI; SHIBATA ATSUSHI |
| PURPOSE:To facilitate the implementation of a device, which has A/D and D/A conversion functions, into an integrated circuit, by using the digital output terminal of an A/D converter and a register circuit as a digital input terminal and a latch circuit for D/A conversion. CONSTITUTION:An A/D converter consists of a comparator 2, a local decoder 3, a register consisting of flip flops 5a-5d, a logic circuit consisting of flip flops 6a-6e, and switching circuits 14a-14d and 15a-15d. In case of D/A conversion, outputs of buffer circuits 13a-13d are released by a switching signal 17, and switching circuits 14a-14d and 15a-15d are switched to apply the digital signal from digital output and input terminals 12 to D terminals, of flip flops 5a-5d, and a strobe signal 16 is applied to Cp terminals, and the register is operated as a latch circuit, and the local decoder 3 is driven to obtain an analogue output. Thus, the device having both conversion functions is made into an integrated circuit easily. | ||||||
| 220 | Code converting device | JP14350180 | 1980-10-13 | JPS5765923A | 1982-04-21 | MORI TOSHIKI; SHIBATA ATSUSHI |
| PURPOSE:To facilitate making a device, which has A/D and D/A conversion functions, into an integrated circuit, by releasing the output of a register and using digital output and input terminals for A/D conversion as digital input terminals and taking output of a local decoder from an analogue output terminal when the device is used for D/A conversion. CONSTITUTION:In cast that a local decoder 3 of an A/D converter is used as a D/A converter, digital output and input terminals 11 for A/D conversion are operated as digital input terminals, and the output of the local decoder 3 is taken out from an analogue output terminal 10. In this case, when a digital signal is applied from digital output and input terminals 11, a switching signal is applied from an A/D and D/A switching signal input terminal 12 to release the output of a register 4 for the purpose of preventing mixture with the output signal of the register 4. Thus, the device having A/D and D/A conversion function is made into an integrated circuit easily without increasing considerably the number of circuits and pins. | ||||||
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