Two-way code converting system |
|||||||
申请号 | JP1547681 | 申请日 | 1981-02-04 | 公开(公告)号 | JPS57129525A | 公开(公告)日 | 1982-08-11 |
申请人 | Fujitsu Ltd; | 发明人 | KARIBE HIROHISA; IKEZAWA MASUSHI; MATSUMURA TOSHIHIKO; FUKUI HIROKAZU; | ||||
摘要 | PURPOSE:To realize the asynchronous action of two-way code conversion, by providing the 1st PLL circuit plus its subordinate 2nd PLL circuit. CONSTITUTION:The 2nd PLL circuit 25 receives clocks CLK1 and CLK2 of different phases which have a comparatively high frequency compared with the clock that is produced from a voltage control type oscillator within the 1st PLL circuit 24. Then one of these two clocks is selected through a clock selecting circuit 31 to be used as a clock CLK3. This clock CLK3 is divided by a frequency divider circuit 32 to produce a clock corresponding to a receiving synchronous signal 27, and the phase comparison is carried out through a phase comparator 30. The clock is consecutively used if the state of phase is satisfactory and then replaced with another clock if the state of phase becomes unsatisfactory. | ||||||
权利要求 | |||||||
说明书全文 |