| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 121 | Switching arrangement for converting analog signals into digital signals and digital signals into analog signals | US751980 | 1976-12-20 | US4118697A | 1978-10-03 | Max Schlichte |
| Apparatus for converting analog to digital signals and vice versa is described wherein a storage capacitor provided at an input of a codec operating in accordance with the iterative method and designed for receiving analog signals to be converted into digital signals is further connected either to a constant current generator or to the digital-to-analog converter of the codec for a period during which a voltage may be applied to the capacitor which correponds to a digital signal that is to be converted into an analog signal and that has been applied to the digital-to-analog converter. A two-wire circuit transmitting analog signals in both directions of transmission is connected to the storage capacitor. The resonance-exchange-of-charge method is used for the transmission of the analog signals. | ||||||
| 122 | Reversible analog-to-digital converter | US715864 | 1976-08-19 | US4112427A | 1978-09-05 | Ernst Hofer; Peter Hirschmann; Klaus Wintzer |
| A method and apparatus for a telecommunication installation is disclosed for converting PAM analog signals into PCM digital signals and vice versa. A conversion circuit which is connected to a telephone station comprises an input register for temporarily storing the incoming PCM digital signals and an output register for temporarily storing the outgoing PCM digital signals. This conversion circuit includes a clock pulse generator which enables a counter to count through all its counter positions upon the appearance of each channel time slot pulse of the incoming PCM channel time slot pulse train. The input register and counter are connected to an intermediate register which in turn is connected to a digital-to-analog converter for converting the incoming PCM digital signal into an analog signal. This analog signal is sent to the receiving unit of the telephone station in a first time interval of the counter. The conversion circuit also comprises an analog comparator which is connected to the transmitting unit of the telephone station for receiving PAM analog signals. This PAM analog signal is converted into a digital signal in the intermediate register during a second time interval of the counter. The converted analog signal is then fed to the output register to be sent to the PCM switching center. Thus, the conversion circuit of this invention is time shared for use in converting both digital and analog signals. | ||||||
| 123 | Reversible analog to digital converter | US709125 | 1976-07-27 | US4056820A | 1977-11-01 | Ernst Hofer |
| A switching arrangement for converting analog signals into digital signals, and vice versa, is described. Conversions between pulse amplitude modulated (PAM) and pulse code modulated (PCM) signals are performed. In telecommunication systems having subscriber stations equipped to transmit and receive analog signals it is necessary to carry out these conversions to facilitate PCM transmission. An analog to digital converter is thus provided at each subscriber station for converting received digital signals into analog signals and analog signals to be transmitted into digital signals; the converter utilizes the iterative principle. | ||||||
| 124 | Overlap PCM coder/decoder with reaction time compensation | US687624 | 1976-05-19 | US4034294A | 1977-07-05 | James Edwin Dalley |
| A PCM coder/decoder circuit is disclosed employing a counter that counts clock pulses until a transmitting ramp voltage equals that of an outgoing speech sample. The encoded count is transmitted in complemented form to the distant station where it is eventually entered into a counter similar to that of the transmitting station. Clock pulses are then applied to the receiving counter until a carry is generated at which time a receiving ramp waveform is disconnected from a decoding capacitor. The counter at the receiving station is enabled prematurely to generate the count so that the "reaction time" of the physical circuit components is compensated for. Compensation of this reaction time is important in reducing the nonlinear distortion that would otherwise be introduced when the ramp waveforms that are employed are of the companded type. The circuit operates in an overlap fashion, encoding and receiving in one field and decoding and transmitting in another field. Control time slots are interspersed between these fields and the control time slot intervals are advantageously employed to augment the code in the counter. | ||||||
| 125 | Non-linear digital-to-analog convertor | US517836 | 1974-10-24 | US3999181A | 1976-12-21 | Jean-Jacques Hirsch |
| Non-linear convertor for converting a data item given in digital form inton analog data item, the value of the digital data item being defined by position digits inside a range of values defined by range digit, characterized in that the convertor comprises a stochastic linear coder receiving the position digits and range digits and supplying a first stochastic data item, an adjustable probability divider whose division ratio is determined by the range digits, receiving that first stochastic data item supplying a second stochastic data item and being followed by a flux-former circuit and a low-pass filter giving the analog output data item. | ||||||
| 126 | Quantity level gauge | US29994072 | 1972-10-24 | US3918035A | 1975-11-04 | ESHRAGHIAN KAMRAN |
| Indicating apparatus comprising a plurality of indicator lamps connected to respective outputs of a plurality of voltage comparators. The comparators have a first input connected to a common input supplied with an input voltage related to a quantity to be measured and a second input connected to respective reference voltages whereby each comparator energizes its respective lamp when the input voltage equals its respective reference voltage.
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| 127 | Analog-to-digital and digital-to-analog converter apparatus | US44489074 | 1974-02-22 | US3883864A | 1975-05-13 | THOMAS ROBERT M |
| PCM encoder-decoder having a digital code generator which counts through a digital count during a comparison period. An analog voltage waveform generator sweeps in a non-linear manner from a maximum negative to a maximum positive voltage during the same period. The digital code generator and analog voltage waveform generator are synchronized so that during each instant of each comparison period they have corresponding values. At the start of each comparison period a sample of an audio voice signal to be encoded is trapped in a capacitor. During a comparison period the sample is compared with the output of the waveform generator. When equality is detected the count of the digital code generator at that instant is stored as a PCM digital signal for transmission with other PCM signals in accordance with known TDM techniques. A PCM digital signal which is received in accordance with known TDM techniques is stored in a register prior to the start of a comparison period. During a comparison period the stored digital signal is compared with the output of the digital code generator. When equality is detected, the voltage of the analog signal from the analog voltage waveform generator at that instant is trapped in a capacitor. At the end of the comparison period the trapped charge is released as a pulse to a low-pass filter. A series of pulses is converted to a continuous audio signal by the low-pass filter.
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| 128 | Encoder-decoder for pcm systems | US25994072 | 1972-06-05 | US3810020A | 1974-05-07 | FORTUNA A; PERSSON H |
| High accuracy at low signal amplitudes is achieved in the encoder section of an encoder-decoder for PCM signals together with low cost by using a feedback linear encoder with a digital compandor, dividing the companding scale into two ranges having an equal number of segments, providing a separate comparator for each range, and using the same set of weights for both comparators. A shift weight is provided to go from the low-level comparison to the high-level comparison, and a ratio-producing network is provided to multiply the effect of each weight by the appropriate expansion factor in the high-level comparator as compared to the low-level comparator.
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| 129 | Digital transient analyzer | US14393961 | 1961-10-09 | US3192519A | 1965-06-29 | ORVAR ANDERSON TAGE |
| 130 | Data handling system and magnetic switching network therefor | US53940455 | 1955-10-10 | US2972136A | 1961-02-14 | PAUL GIESELER LUTHER |
| 131 | Digitizer | US16646250 | 1950-06-06 | US2631778A | 1953-03-17 | PIPER CHARLES A; BROWN LOWELL R |
| 132 | Fieldbus adapter and method of using fieldbus adapter | EP12176034.2 | 2012-07-11 | EP2551735A3 | 2016-01-13 | Washiro, Mitsuhiro |
A fieldbus adapter (2) connected between a fieldbus (3) that handles a digital signal and a field device (1A-1D) that handles an analog signal, the fieldbus adapter (2) comprising a first connection unit (2b) detachably connected to the fieldbus (3), a second connection unit (2a) detachably connected to the field device (1A-1D), and a conversion unit (23) provided between the first connection unit (2b) and the second connection unit (2a), the conversion unit (23) bidirectionally converting the digital signal handled by the fieldbus (3) and the analog signal handled by the field device (1A-1D).
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| 133 | Fieldbus adapter and method of using fieldbus adapter | EP12176034.2 | 2012-07-11 | EP2551735A2 | 2013-01-30 | Washiro, Mitsuhiro |
A fieldbus adapter (2) connected between a fieldbus (3) that handles a digital signal and a field device (1A-1D) that handles an analog signal, the fieldbus adapter (2) comprising a first connection unit (2b) detachably connected to the fieldbus (3), a second connection unit (2a) detachably connected to the field device (1A-1D), and a conversion unit (23) provided between the first connection unit (2b) and the second connection unit (2a), the conversion unit (23) bidirectionally converting the digital signal handled by the fieldbus (3) and the analog signal handled by the field device (1A-1D).
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| 134 | OFFSET CALIBRATION SYSTEM | EP03731031.5 | 2003-04-17 | EP1510007B1 | 2006-10-11 | GEALOW, Jeffrey , C.; BARBER, Thomas, J., Jr.; FERGUSON, Paul, F., Jr.; HAURIE, Xavier, S. |
| An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit. | ||||||
| 135 | CONVERTISSEUR ANALOGIQUE-NUMERIQUE ET NUMERIQUE-ANALOGIQUE | EP00972525.0 | 2000-11-10 | EP1332555B1 | 2005-10-26 | WOUTERS, Sietse, Engelbregt |
| The invention concerns a coder-decoder comprising an analog-to-digital converter and produced in the form of a discrete electronic component (2), including: an analog-to-digital conversion circuit (14) for converting said input analog signal into a sequence of digital samples; an output stage (16) for supplying said sequence in serial form outside said component (2); a first signal detection circuit (22, 24, 26, 28) to indicate outside said component the presence or the absence of significant data in said sequence. | ||||||
| 136 | OFFSET CALIBRATION SYSTEM | EP03731031 | 2003-04-17 | EP1510007A4 | 2005-07-27 | GEALOW JEFFREY C; BARBER THOMAS J JR; FERGUSON PAUL F JR; HAURIE XAVIER S |
| An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit. | ||||||
| 137 | OFFSET CALIBRATION SYSTEM | EP03731031.5 | 2003-04-17 | EP1510007A1 | 2005-03-02 | GEALOW, Jeffrey , C.; BARBER, Thomas, J., Jr.; FERGUSON, Paul, F., Jr.; HAURIE, Xavier, S. |
| An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit. | ||||||
| 138 | INTEGRATED CIRCUIT FOR CONDITIONING AND CONVERSION OF BI-DIRECTIONAL DISCRETE AND ANALOG SIGNALS | EP01987488.2 | 2001-10-24 | EP1410307A2 | 2004-04-21 | YOUNIS, Mohamed; ERNST, James, W. |
| An integrated circuit chip (105) for interfacing a digital computer (103) to sensors (101) and controlled devices (107) can be configured to accept and provide a variety of analog and discrete input and output signals. The circuit includes a plurality of signal conditioning cells (111), a plurality of signal conversion cells (113), and input and output signal multiplexors. | ||||||
| 139 | CONVERTISSEUR ANALOGIQUE-NUMERIQUE ET NUMERIQUE-ANALOGIQUE | EP00972525.0 | 2000-11-10 | EP1332555A1 | 2003-08-06 | WOUTERS, Sietse, Engelbregt |
| The invention concerns a coder-decoder comprising an analog-to-digital converter and produced in the form of a discrete electronic component (2), including: an analog-to-digital conversion circuit (14) for converting said input analog signal into a sequence of digital samples; an output stage (16) for supplying said sequence in serial form outside said component (2); a first signal detection circuit (22, 24, 26, 28) to indicate outside said component the presence or the absence of significant data in said sequence. | ||||||
| 140 | Method and apparatus for analog to digital conversion | EP94306580.5 | 1994-09-07 | EP0650260B1 | 2000-08-09 | Stewart, Brett; Moyal, Miki |
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