| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | Driver arrangement and method for providing an analog output signal | US15302482 | 2015-03-27 | US10063248B2 | 2018-08-28 | Luigi Di Piro; Riccardo Serventi; Paolo D'Abramo; Edoardo Biagi; Luca Fanucci |
| A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11). | ||||||
| 102 | RECONFIGURABLE TRANSCEIVERS | US15413993 | 2017-01-24 | US20180019759A1 | 2018-01-18 | Haim Mendel WEISSMAN; Mahim RANJAN |
| A transceiver including: a reconfigurable circuit including a plurality of units including at least a converter, the converter including: a digital-to-analog converter (DAC); successive approximation register (SAR) logic configured to selectively couple to the DAC; and a plurality of switches configured to reconfigure the plurality of units of the reconfigurable circuit to operate the transceiver in a receive mode or transmit mode. | ||||||
| 103 | DRIVER ARRANGEMENT AND METHOD FOR PROVIDING AN ANALOG OUTPUT SIGNAL | US15302482 | 2015-03-27 | US20170041017A1 | 2017-02-09 | Luigi Di Piro; Riccardo Serventi; Paolo D'Abramo; Edoardo Biagi; Luca Fanucci |
| A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11). | ||||||
| 104 | Fieldbus adapter and method of using fieldbus adapter | US13556371 | 2012-07-24 | US08963749B2 | 2015-02-24 | Mitsuhiro Washiro |
| A fieldbus adaptor connected between a fieldbus that handles a digital signal and a field device that handles an analog signal, the fieldbus adaptor comprising a first connection unit detachably connected to the fieldbus, a second connection unit detachably connected to the field device, and a conversion unit provided between the first connection unit and the second connection unit, the conversion unit bidirectionally converting the digital signal handled by the fieldbus and the analog signal handled by the field device. | ||||||
| 105 | Data-driven noise reduction technique for analog to digital converters | US14163560 | 2014-01-24 | US08896476B2 | 2014-11-25 | Pieter Joost Adriaan Harpe |
| A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τMV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τMV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output. | ||||||
| 106 | SYSTEM INCLUDING FEEDBACK CIRCUIT WITH DIGITAL CHOPPING CIRCUIT | US13527120 | 2012-06-19 | US20120262317A1 | 2012-10-18 | Mario Motz; Udo Ausserlechner |
| A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The digital to analog converter circuit is configured to convert an error signal into an analog signal that is received by the second circuit to reduce ripple error. | ||||||
| 107 | System including feedback circuit with digital chopping circuit | US12717294 | 2010-03-04 | US08203471B2 | 2012-06-19 | Mario Motz; Udo Ausserlechner |
| A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The chopping circuit is configured to receive the digital output signals and provide error signals that represent ripple error in the digital output signals. The integrator circuit is configured to accumulate the error signals and provide an accumulated error signal. The digital to analog converter circuit is configured to convert the accumulated error signal into an analog signal that is received by the second circuit to reduce the ripple error. | ||||||
| 108 | Digital-analog-conversion circuit having function of automatic offset adjustment | US10367966 | 2003-02-19 | US20030179118A1 | 2003-09-25 | Tohru Mizutani; Hiromi Nanba; Atsushi Matsuda; Atsushi Hitaka; Masashi Okubo; Yoshinori Yoshikawa; Kenichi Minobe |
| An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal. | ||||||
| 109 | Analog to digital converter having a digital to analog converter mode | US09458539 | 1999-12-09 | US06359575B1 | 2002-03-19 | Niels Knudsen |
| An analog to digital (A/D) converter which includes A/D converter and D/A converter modes. The A/D converter includes an internal digital to analog (D/A) converter (DAC) that may be used in a feedback loop during A/D operations (in the A/D mode), and may be used as a stand-alone D/A converter in the D/A mode. The present invention also takes advantage of advanced calibration techniques available for the internal D/A converter of the A/D converter. A processing unit may be coupled to the output of the internal A/D converter. The processing unit or a separate computer system may perform a calibration function in the A/D mode to generate linearity error correction information for correcting linearity errors in the internal D/A converter. The linearity error correction information may be used in configuring a linearity error correction device implemented by the processing unit. In the A/D mode, the processing unit may implement linearity error correction and a decimation function during A/D conversion. In the D/A mode, the processing unit also may implement linearity error correction functions as well as other functions during D/A conversion. The A/D converter may also include switching elements used in configuring the A/D converter in either the A/D mode or the D/A mode. | ||||||
| 110 | Reducing the number of trim links needed on multi-channel analog integrated circuits | US329590 | 1994-10-26 | US5596322A | 1997-01-21 | Douglas G. Marsh; Robert H. Vaiden |
| A method and structure for automatically calibrating various paths within multi-channel analog integrated circuits is disclose. The invention calls for digital signal processing circuitry to correct for absolute gain differences in the multiple channels. A first reference channel is precision trimmed at manufacture and used by the digital processing circuitry as a reference for channel gain calibration. When the circuit is powered for use, the other channels are calibrated based on the trimmed and calibrated reference. The need for providing the circuitry to precision trim all other channels but one is avoided by this invention. | ||||||
| 111 | Circuit configuration for a D/A and A/D converter | US195725 | 1994-02-14 | US5493300A | 1996-02-20 | Walter Eiler; Ruediger Gertner |
| Using only one R2R network, driven by a digital logic, it is possible to implement both a D/A and A/D converter, An existing stabilized voltage V.sub.cc is used instead of a separate reference voltage source. The D/A and A/D converter is calibrated with this voltage and an operational amplifier circuited as a comparator. Starting with the known voltage value V.sub.cc and the assigned bit combination, it is possible to measure analog voltages from analog voltage sources using further operational amplifiers circuited as comparators. | ||||||
| 112 | Network swappers and circuits constructed from same | US45815 | 1993-04-08 | US5404143A | 1995-04-04 | Robert J. Distinti |
| An n-bit analog processing circuit constructed with network swappers has n stages and an input port for inputting an analog signal to be processed. Each of the n stages includes first and second reference input ports, at least one swappable network having first and second terminals, and a switching element that is responsive to a digital input signal for varying a connectivity of the first and second terminals with respect to the first and second reference input ports. Each of the n networks has a primary electrical characteristic that is binarily weighted with respect to others of the networks. The primary electrical characteristic may be resistance, capacitance, capacitive reactance, inductance, inductive reactance, voltage potential, gain, transconductance, superconductance, time delay, permeability, electrical or optical conductor length, and/or winding turns. A characteristic of an analog signal appearing at an output port is a function of an analog signal applied between the first and second reference input ports of a most significant stage, and is also a function of an n-bit digital signal (binary or Gray code) that is applied to the n-stages. | ||||||
| 113 | Analog-to-digital and digital-to-analog converter | US305383 | 1989-02-01 | US4908620A | 1990-03-13 | Akihiko Fujisawa |
| An analog-to-digital and digital-to-analog converter includes an array of capacitors each being differently weighed from the others, one electrode of each of the capacitors being connected to a common node. Switches are provided for selectively applying, in response to a first control signal, an analog input applied to an analog input terminal and a plurality of reference voltages to the other electrode of the capacitors. A comparator has a pair of input terminals whose inverting and non-inverting inputs are selectively switched over with respect to polarity in response to a second control signal. The comparator compares a voltage appearing on the node and applied to one of the input terminals and one of the reference voltages applied to the other input terminal. An analog output terminal is connected to the output of the comparator. A successive comparison register sequentially takes in outputs of the comparator in response to a third control signal. A latch selectively takes in and temporarily holds one of digital inputs applied via a digital input terminal and outputs of the successive comparison register in response to the second control signal. A digital output terminal is connected to the output of the latch. The first and third control signals are generated by a timing generating circuit in response to an output of the latch. | ||||||
| 114 | Ratio independent cyclic A/D and D/A conversion using a reciprocating reference approach | US655642 | 1984-09-28 | US4622536A | 1986-11-11 | Cheng-Chung Shih; Paul R. Gray |
| An algorithmic analog-to-digital and digital-to-analog converter 10 combines the techniques of switched capacitor cyclic conversion by using first and second amplifiers 31, 32 with capacitors C.sub.1, C.sub.1 ', C.sub.2, C.sub.2 ', C.sub.3, C.sub.3 ', C.sub.4, C.sub.4 ', C.sub.5, C.sub.5 ' communicating with the inputs of said amplifiers 31, 32 and between the inputs and outputs of said amplifiers 31, 32, and the techniques of reference voltage refreshing. The performance of the converter 10 is capacitor ratio-independent. Because of the ratio-independent aspect, very small component values can be used, and as a result, the die area required for the circuitry can be quite small. | ||||||
| 115 | Method for eliminating the zero point error in an iterative analog-digital converter | US285625 | 1981-07-21 | US4468651A | 1984-08-28 | Robert Lechner; Frithjof von Sichart; Peter Picard |
| A zero equalization capacitor is connected to a first input of the comparator K, and at the beginning of the equalization phase, a voltage value of zero is placed at both comparator inputs, and a feedback network RN is connected between the comparator output and the capacitor, whereby the capacitor is charged to such a degree that the output signal of the comparator arrives at the decision threshold between the equality or inequality of the comparator inputs. | ||||||
| 116 | Bi-polar electronic signal converters with single polarity accurate reference source | US187442 | 1980-09-15 | US4445111A | 1984-04-24 | Steven D. Swift; Jonathan J. Parle; David A. Gunderson |
| Bi-polar electronic signal converters, such as analog-to-digital or digital-to-analog converters, with a single polarity accurate reference source are disclosed. In one polarity direction, the accurate reference source is used in a conventional manner to transform the signal to be converted from one form (e.g., analog) to the other form (e.g., digital). In the other polarity direction, an inaccurate reference source is used in a similar conventional manner to convert the signal from one form to the other form. Periodically, the accurate and the inaccurate reference sources are compared to determine a correction multiplier. The correction multiplier is used during conversions using the inaccurate reference source to compensate for the inaccuracy of the inaccurate reference source. | ||||||
| 117 | .mu.-Law/A-law PCM CODEC | US252600 | 1981-04-09 | US4404544A | 1983-09-13 | Mirmira R. Dwarakanath |
| In a PCM CODEC, a binary-weighted charge redistribution capacitor array is designed to be configured for either .mu.-law or A-law coding. Selection of one or the other coding configuration is achieved by controlling a single gate circuit. A unique cascaded switch arrangement ensures that when selected capacitors representative of a specified coding segment are connected to a reference voltage source, the next successive capacitor of the array is automatically connected to a variable source that provides a voltage representative of a step within the specified segment. | ||||||
| 118 | Dual bandwidth autozero loop for a voice frequency CODEC | US170041 | 1980-07-18 | US4350975A | 1982-09-21 | Yusuf A. Haque; Richard W. Blasco |
| An autozero loop for eliminating offsets in the analog to digital converter section of a voice frequency coder-decoder (CODEC) utilizing an array of capacitors and a linear resistor string. The autozero loop functions with a relatively small time constant to null offsets quickly during the power-up phase of CODEC operation and with a higher time constant after the power-up phase. A dual bandwidth sub-circuit in the loop is connected to a voltage generator and controlled by signals from a logic circuit to operate at different bandwidths and thus provide different offset cancelling feedback signals during the power-up and normal operating phases. | ||||||
| 119 | Asynchronous reversible analog to digital converter | US925787 | 1978-07-18 | US4160243A | 1979-07-03 | Takao Moriya; Masao Yamasawa; Hirohisa Gambe |
| An asynchronous signal processing circuit device having an A-D converter and a D-A converter in which a single ladder voltage generating circuit is commonly or jointly used by changing over a multiplexer during both the A-D and the D-A conversion processing. The asynchronous signal processing circuit device according to the present invention further comprises an interrupt signal generating circuit which produces an inhibit signal so as to provide a predetermined inhibit period during which the interruption by the second signal processing circuit to the first signal processing circuit is inhibited, thus preventing a misoperation of the asynchronous signal processing circuit device at the time of switching over the converters. | ||||||
| 120 | Circuit arrangement for the transmission of digital signals between subscriber stations of a time multiplex telecommunications network | US837297 | 1977-09-27 | US4145574A | 1979-03-20 | Klaus Wintzer |
| In a PCM time multiplex telecommunications network the digital signal input of the coder/decoder of each subscriber station has an individually controllable receiving memory connected to the input of the coder/decoder, and the digital signal output of the respective coder/decoder has an individually controllable transmitting memory connected thereto. The control of the signal receipt and transmission by the coder/decoder takes place at different points in time than the receipt of PCM signals by the receiving memory, and the transmission of PCM signals by the transmitting memory. | ||||||
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