- H03M1/001： .{模拟/数字/模拟的转换}
- H03M1/002： .{节约能量的方法}
- H03M1/004： .{可重构模拟/数字或数字/模拟转换器(H03M1/02优先)}
- H03M1/02： .可逆模/数转换器
- H03M1/04： .应用随机技术的
- H03M1/06： .连续地补偿或防止物理参数有害影响(周期性地,例如.通过使用多个存储修正值的入H03M1/10)
- H03M1/10： .校正或测试
- H03M1/12： .模/数转换器(H03M1/001至H03M1/004且H03M1/02至H03M1/10优先)
- H03M1/66： .数/模转换器(H03M1/001至H03M1/004且H03M1/02至H03M1/10优先)
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | Resolution-boosted sigma delta analog-to-digital converter | EP14001697.3 | 2014-05-14 | EP2811654A3 | 2014-12-24 | Trampitsch, Gerd |
A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to "residual quantization error," which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.
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| 142 | ANALOG-DIGITAL CONVERTER AND SOLID-STATE IMAGE CAPTURE DEVICE | EP12866477.8 | 2012-12-14 | EP2809008A1 | 2014-12-03 | SUGAWA, Shigetoshi |
To obtain accurate digital data while using a successive approximation system when performing analog-to-digital conversion processing in a plurality of steps. There is provided an AD converter including a ramp waveform signal generation unit (14) that generates a ramp voltage based on a count signal from a counter (15), a signal conversion unit (13), and a control unit (18), in which the signal conversion unit (13) includes a sample-and-hold circuit that holds an input signal voltage, a successive approximation capacitance group (16) that outputs a plurality of bias voltages according to a connection combination of a predetermined number of capacitances having different capacitance values, and a comparison unit (17) that compares one of the ramp voltage and the bias voltage with the signal voltage, and the control unit (18) generates a digital signal of the signal voltage based on a comparison result by the comparison unit (17) of the bias voltage and the signal voltage and a comparison result by the comparison unit (17) of the ramp voltage and the signal voltage while acquiring data for calibration of the successive approximation capacitance group (16) based on the connection combination of the capacitances and the ramp voltage. |
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| 143 | Two-stage analog-to-digital converter for high-speed image sensor | EP12179815.1 | 2012-08-09 | EP2696506A1 | 2014-02-12 | Medeiro Hidalgo, Fernando; DomÍnguez Castro, Rafael |
The present invention relates to a two- or multiple-stage analog to digital converter (300). The converter preferably includes an incremental ADC (200) in the first stage. The incremental ADC (200) comprises an integrator (210) and a comparator (220). After the predefined number of comparisons performed by the comparator (220), the output of the integrator (210) appropriately scaled (g) is provided to the second stage (310, 320, 330) where it is further sampled (320). In particular, the scaling gain (310) is inversely proportional to the integrator gain (g). The second ADC (330) performs the conversion of the remaining least significant bits (D2) and then the output of both stages (D1, D2) is combined (340, 350). Moreover, a calibration and correction approaches are provided for the multi-stage ADC.
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| 144 | DIGITAL TO ANALOG CONVERTER CIRCUITS AND METHODS | EP11847104.4 | 2011-12-07 | EP2649729A1 | 2013-10-16 | CYRUSIAN, Sasan |
| The present disclosure provides for improved DAC circuits and methods. In one embodiment, a digital-to-analog converter receives a digital signal and outputs a first analog output signal corresponding to the digital signal. A current buffer receives the first analog output signal and generates an analog output current. The current output digital-to analog converter and the current buffer are constructed on an integrated circuit, and the analog output current is coupled to a pin of the integrated circuit. The pin of the integrated circuit receives the analog output current and provides the analog output current to additional circuitry external to the integrated circuit. | ||||||
| 145 | CONVERTER CIRCUIT, ANALOG/DIGITAL CONVERTER, AND METHOD FOR GENERATING DIGITAL SIGNALS CORRESPONDING TO ANALOG SIGNALS | EP07744949.4 | 2007-06-08 | EP2037583B1 | 2012-08-08 | KAWAHITO, Shoji |
| A charge in accordance with an analog signal (Vi) is stored in each of first and second capacitors (25,27). A digital signal (VDIGN) having digital values (e.g., D1,D0) corresponding to the analog signal (Vi) is generated. The second capacitor (27) is connected between the output (21c) of an operational amplifier circuit (21) and an inverting input (21a) thereof, and an analog signal (VD/A) in accordance with the digital signal (VDIGN) is supplied to an end (25a) of the first capacitor, so that a first converted value (VOUT1) is developed at the output (21c) of the operational amplifier circuit (21). The first capacitor (25) and a third capacitor (33) are connected between the output (21c) of the operational amplifier circuit (21) and the inverting input (21a) thereof, and the analog signal (VD/A) is supplied to an end (27a) of the second capacitor, so that a second converted value (VOUT2) is developed at the output (21c) of the operational amplifier circuit (21). | ||||||
| 146 | CONVERTER CIRCUIT, ANALOG/DIGITAL CONVERTER, AND METHOD FOR GENERATING DIGITAL SIGNALS CORRESPONDING TO ANALOG SIGNALS | EP07744949 | 2007-06-08 | EP2037583A4 | 2010-05-12 | KAWAHITO SHOJI |
| 147 | DECODER AND DECODING METHOD | EP99959802 | 1999-12-14 | EP1071217A4 | 2001-12-12 | IKEDA TAMOTSU; MIYAUCHI TOSHIYUKI |
| The deterioration in the error characteristics at transition points in a transmission system is suppressed. A first adder calculates the SM value at a transition from state 00 to state 00 and produces output for a comparator. A second adder calculates the SM value at a transition from state 01 to state 00 and produces output for the comparator. The comparator compares such SM values, selects a maximum-likelihood pass, and sends the results to a set/reset register. An ACS controller detects the unique determination of transition of the state of fixed information (TAB1), outputs a reset signal to the set/reset register storing the SM value in the state to reset the resist value to 0, and outputs a set signal to the set/reset registers storing the SM values other than values corresponding to state 00 of the fixed information (TAB1) to set the resist value to the MAX value. | ||||||
| 148 | DECODER AND DECODING METHOD | EP99959802.2 | 1999-12-14 | EP1071217A1 | 2001-01-24 | Ikeda, Tamotsu; Miyauchi, Toshiyuki |
The deterioration of an error characteristic obtained at a point where a transfer method is changed is suppressed. A first adder calculates a SM value obtained when the state 00 is changed to the state 00, and outputs it to a comparator. A second adder calculates a SM value obtained when the state 01 is changed to the state 00, and outputs it to the comparator. The comparator compares the SM values, selects a path having the larger likelihood, and outputs to a register having a set and a reset. An ACS controller detects a condition in which the state transition of fixed information TAB1 is uniquely determined, and outputs a reset signal to the register having a set and a reset, which stores the SM value of that state, to set the value of the register to zero. The ACS controller 85 also outputs set signals to registers having sets and resets, which store the SM values of the states other than the state 00 of the fixed information TAB1, to set them to the maximum value. |
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| 149 | APPARATUS FOR CONVERTING AN ANALOGUE BALANCED SIGNAL TO A DIGITAL SIGNAL | EP87902169.9 | 1987-03-05 | EP0263140B1 | 1990-10-03 | HAULIN, Tord, Lennart |
| An apparatus for converting an analogue, balanced signal (VIN+, VIN-) to a digital signal by charge redistribution in a plurality of capacitors (1-5, 1'-5'). These are grouped in two sets and at least during an approximating phase can be selectively connected to two different reference voltages (VR, earth) with the aid of switches (6-10, 6'-10'). The sets of capacitors are each arranged to act on the potential at their respective points (13, 13') during an approximating phase, and a comparator (15) is adapted for comparing the potentials at these points. The switches are controlled by a means (18) for sampling and approximating logic which generates digital control words in response to the comparison result, of the comparator. | ||||||
| 150 | APPARATUS FOR CONVERTING AN ANALOGUE BALANCED SIGNAL TO A DIGITAL SIGNAL | EP87902169.0 | 1987-03-05 | EP0263140A1 | 1988-04-13 | HAULIN, Tord, Lennart |
| L'appareil ci-décrit sert à convertir un signal symétrique analogique (VIN+, VIN-) en un signal numérique par redistribution de charge dans plusieurs condensateurs (1-5, 1'-5'). Ces derniers sont groupés en deux groupes et peuvent, durant au moins une phase d'approximation, être sélectivement connectés à deux tensions de référence différentes (VR, terre) à l'aide de commutateurs (6-10, 6'-10'). Les groupes de condensateurs agissent chacun sur le potentiel au niveau de leur points correspondants (13, 13') durant une phase d'approximation et un comparateur (15) compare les potentiels en ces points. Les commutateurs sont commandés par un organe (18) à fonction logique d'échantillonage et d'approximation produisant des mots de commande numériques en réponse au résultat comparatif fourni par le comparateur. | ||||||
| 151 | Monolithisch integrierbares R-2R-Netzwerk | EP80107406.3 | 1980-11-27 | EP0053193B1 | 1985-04-17 | Struthoff, Holger, Ing.-grad. |
| 152 | Générateur de tension codée à transfert de charges, codeur et décodeur analogique-numérique comportant un tel générateur | EP80401781.2 | 1980-12-12 | EP0031751A1 | 1981-07-08 | Benoit-Gonin, Roger; Berger, Jean-Luc; Coutures, Jean-Louis |
Des allers-retours successifs des charges entre les grilles Go et G2 permettent d'obtenir sous G1 et G2 des quantités de charges égales à QR, QR/2, QR/22 ... QR/2i. Un dispositif de lecture des charges relié à G2 et G4 élabore des tensions VR et VRi = ao. VR+a1· VR/2 + ... + ai-1 VR/2i-1+ VR/2i qui sont comparées avec un échantillon de tension à coder Vx afin de déterminer par approximations successives les coefficients ao ... an égaux à 0 ou à 1 tels que Vx = ao· VR+a1· VR/2 + ... + an·VR/2n. Selon la valeur de ai, chaque quantité de charges QR/2i stockée sous G1 est évacuée sous De ou stockée sous G3 puis transférée sous G4. |
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| 153 | Abtastanordnung für den Codeträger einer Schaltgewichtseinrichtung in einer Waage zur Erweiterung des Wägebereichs | EP79103845.8 | 1979-10-08 | EP0009821A1 | 1980-04-16 | Knothe, Erich; Melcher, Franz-Josef; Oldendorf, Christian |
Abtastanordnung für den Codeträger (6) einer Schaltgewichtseinrichtung in einer Waage zur Erweiterung des Wägebereichs, wobei der Codeträger die Stellung der Schaltgewichtseinrichtung analog anzeigt und in Abhängigkeit von den möglichen Schaltstellungen mehrere nebeneinanderliegende Codespuren (S 1 bis S 5) aufweist, die in magnetoelektronisch und/oder optoelektronisch wirksame und unwirksame Abschnitte (7,8) unterteilt sind und mit einer aus mehreren Sender-Empfänger-Einheiten (1,1' bis 5,5') aufweisenden Abtastung korrespondieren, welche an eine Anzeige und/oder Steuereinrichtung angeschlossen ist. Um die bei der Miniaturisierung der Abtastanordnungen auftretenden Probleme der störenden Überlagerung der Sender-Empfänger-Signale benachbarter Codespuren zu lösen, sind die den einzelnen Codespuren (S 1 bis S 5) zugeordneten Sender-Empfänger-Einheiten (1,1' bis 5,5') in Längsrichtung der Codespuren (S 1 bis S 5) versetzt zueinander angeordnet und die magnetoelektronisch und/oder optoelektronisch wirksamen und unwirksamen Abschnitte (7,8) der jeweiligen Codespuren sind in entsprechender Weise zueinander versetzt. |
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| 154 | Capteur optoélectronique de déplacement longitudinal | EP79400428.3 | 1979-06-27 | EP0007267A1 | 1980-01-23 | Marchal, Michel |
Capteur optoélectronique de déplacement longitudinal, caractérisé en ce qu'il comporte des moyens de filtrage et de protection contre les surtensions ; des moyens d'émission 100 et de réception 200 de rayons infrarouges ; un moyen d'occultation 300 de l'émission de rayons infrarouges ; des moyens de codage 400 en code binaire réfléchi des signaux issus des moyens de réception des rayons infrarouges ; des moyens de transformation 500 des signaux codes en code binaire réfléchi de manière qu'en sortie du capteur on dispose d'un nombre binaire ordinaire représentatif de la grandeur variable du déplacement |
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| 155 | 고온 측정법을 위한 완전 차동 증폭 | KR1020177020560 | 2015-12-28 | KR1020170097197A | 2017-08-25 | 머레이도날드에프 |
| 본개시물은증폭섹션에대한개선들을통해, 고온계의신호대잡음비를개선하고, 샘플링속도를증가시키고, 동적범위를증가시키기위한시스템들, 방법들, 및장치들을기술한다. 특히, 단일스테이지비-차동증폭기들은잡음의비례하는증가없이이득을증가시키는차동증폭기회로로대체될수 있다. 차동증폭기회로는광 검출기로부터차동전류를수신하고트랜스컨덕턴스이득을가지는것에응답하여차동전압출력을생성하는, 병렬로배열된트랜스임피던스증폭기회로들의쌍을포함할수 있다. | ||||||
| 156 | 마이크로―코딩된 시퀀서를 구비한 아날로그―디지털 변환 장치 | KR1020177006669 | 2015-10-16 | KR1020170071474A | 2017-06-23 | 바틀링,제임스이.; 우제우다,이고르; 킬저,케빈 |
| 마이크로-코딩된시퀀서는중앙처리유닛(CPU)과는독립적으로복합변환시퀀스들을제어한다. 마이크로-코딩은새로운처리단계를쉽게추가하거나기존프로세스단계들을업데이트하는것을제공한다. 아날로그-디지털변환기(ADC) 또는충전시간측정유닛(CTMU)과같은아날로그-디지털변환모듈과디지털처리회로와결합된이러한프로그램가능시퀀서는, 마이크로-코딩된시퀀서와결합하여 CPU와독립적으로작업하도록구성될수 있다. 이것에의해, CPU 및다른고전력모듈들이저전력슬립모드에있을때에도저전력모드들의자급자족동작이제공된다. 이러한주변장치는데이터수집및 그것의처리를실행할수 있고, 그리고필요시에만 CPU를깨우므로전력을절약할수 있다. 또한, 이주변장치는 CPU 처리를필요로하지않으므로, CPU에의한제어를요구하는시간중요애플리케이션들은더 효율적이면서도동작오버헤드는부담이덜하게동작할수 있다. | ||||||
| 157 | 이득 부스팅에 의한 오버샘플된 아날로그-디지털 변환기들의 대역폭 확장 | KR1020160126663 | 2016-09-30 | KR1020170040108A | 2017-04-12 | 로라,코네사-페라레자; 페톤,수사나; 스트라우스니그,디에트마; 위에스바우더,안드리아스 |
| 디지털화시스템은센서또는다른소자로부터하나이상의아날로그신호를수신하고아날로그신호들을하나이상의디지털신호로변환하도록동작한다. 아날로그-디지털변환기는루프필터, 양자화기및 하나이상의피드백디지털-아날로그변환기를포함한다. 이득소자는아날로그-디지털변환기의대역폭을확장하기위해신호처리경로의상이한점들을따라계수들을제공한다. 이득소자는정상동작모드에서처리되는다른신호들보다더 높은주파수대역에서확장된동작모드에서신호를처리하기위해잡음전달함수를보존하면서아날로그-디지털변환기의신호전달함수를수정할수 있다. | ||||||
| 158 | 축차 근사 레지스터 아날로그 디지털 변환기와 이를 포함하는 반도체 장치 | KR1020150135483 | 2015-09-24 | KR1020170036387A | 2017-04-03 | 백승엽; 신은석; 최병주 |
| 비동기 SAR ADC가개시된다. 상기비동기 SAR ADC는샘플링클락신호와제어코드에기초하여주파수를결정하고, 상기결정된주파수에대응하는출력클락신호를생성하는링 오실레이터와, 상기출력클락신호의주파수에기초하여상기제어코드를생성하는컨트롤러를포함한다. | ||||||
| 159 | 출력 피크 전류를 분산할 수 있는 이미지 센서와 이를 포함하는 이미지 처리 시스템 | KR1020150083430 | 2015-06-12 | KR1020160146323A | 2016-12-21 | 이한수; 채희성; 김경민; 김다솜; 김선중; 정승훈 |
| 이미지센서가개시된다. 상기이미지센서는제1픽셀로부터출력된제1아날로그픽셀신호를제1디지털신호들로변환하는제1아날로그-디지털변환기와, 제2픽셀로부터출력된제2아날로그픽셀신호를제2디지털신호들로변환하는제2아날로그-디지털변환기와, 제1이네이블제어신호에응답하여상기제1디지털신호들중에서제1위치의제1비트값을출력하는제1출력회로와, 제2이네이블제어신호에응답하여상기제2디지털신호들중에서상기제1위치와동일한제2위치의제2비트값을출력하는제2출력회로를포함한다. | ||||||
| 160 | 연속적인 근사화 레지스터 아날로그-디지털 변환기에서 공급기 및/또는 비교기 공통 모드 전압의 폐루프 제어를 위한 방법 및 장치 | KR1020157026493 | 2014-02-21 | KR101587484B1 | 2016-01-21 | 나가라잔,카르틱; 알라디,디네쉬,제이 |
| 본명세서에서설명되는실시예들은연속적인근사화레지스터아날로그-디지털변환기및 비교기공통모드전압을위한공급기전압을제어하기위한방법및 장치를제공한다. 이방법은연속적인근사화레지스터변환시간을측정하는단계; 연속적인근사화레지스터변환시간을원하는변환시간에비교하는단계; 및필요한경우, 공급기및/또는비교기공통모드전압중 적어도하나의폐루프조정을수행하는단계를포함한다. 장치는공통모드전압및 레귤레이터정정모듈로구성된다. 공통모드전압및 레귤레이터정정모듈은위상주파수검출기, 충전펌프를포함하고, 트랜스컨덕턴스셀(transconductance cell)을포함할수 있다. | ||||||
