| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 模数转换器 | CN201280072784.8 | 2012-05-30 | CN104303420B | 2017-12-26 | H.拉克达瓦拉; R.阿肖科; D.奧菲尔; A.埃坎; J.H.卢; G·埃士尔 |
| 一种技术包括：接收模拟信号；以及产生具有指示模拟信号的量值的定时的至少一个第二信号。该技术包括：获取定时的多个测量值，其中所述测量值根据随机分布变化；以及至少部分地基于测量值提供模拟信号的数字表示。 | ||||||
| 2 | 模数转换器 | CN201280072784.8 | 2012-05-30 | CN104303420A | 2015-01-21 | H.拉克达瓦拉; R.阿肖科; D.奧菲尔; A.埃坎; J.H.卢; G·埃士尔 |
| 一种技术包括：接收模拟信号；以及产生具有指示模拟信号的量值的定时的至少一个第二信号。该技术包括：获取定时的多个测量值，其中所述测量值根据随机分布变化；以及至少部分地基于测量值提供模拟信号的数字表示。 | ||||||
| 3 | 随机编码非模拟到数字的转换 | CN201410719994.2 | 2014-12-02 | CN104702283A | 2015-06-10 | T·M·麦克勒奥德 |
| 本发明涉及随机编码非模拟到数字的转换。一种用于对随机信号编码模拟信号的方法和系统，编码的信号然后由模拟到数字转换器转换成数字信号，所述模拟到数字转换器随后从已编码的信号解码对应于模拟信号的数字信号。上述随机信号可成形为高斯正态曲线的噪声信号。编码处理由乘法电路执行，其相乘模拟信号和随机信号，产生模拟到数字转换的乘积信号。在模拟到数字转换期间，所述乘积信号被进行解码。使用算术运算(其可是和平方根函数或根均方函数)进行解码。然后解码后的信号被映射以解决偏移误差、增益误差和端点调整。其结果是对应于该模拟信号的解码数字信号。 | ||||||
| 4 | ANALOG-TO-DIGITAL CONVERTER | EP12877696.0 | 2012-05-30 | EP2856650A1 | 2015-04-08 | LAKDAWALA, Hasnain; ASHOKE, Ravi; OFIR, Degani; ERKAN, Alpman; LU, Julia H.; ESHEL, Gordon |
| A technique includes receiving an analog signal and generating at least one second signal that has a timing indicative of a magnitude of the analog signal. The technique includes acquiring a plurality of measurements of the timing, where the measurements vary according to a stochastic distribution; and providing a digital representation of the analog signal based at least in part on the measurements. | ||||||
| 5 | メモリの確率的スイッチングに基づいてADCを設計するためのシステムおよび方法 | JP2014532036 | 2012-09-21 | JP5826940B2 | 2015-12-02 | ベンカトラマン、スブラマニアン; レビン、ジェフリー・アレキサンダー |
| 6 | System and method for designing adc based on probabilistic switching memory | JP2014532036 | 2012-09-21 | JP2014526861A | 2014-10-06 | ベンカトラマン、スブラマニアン; レビン、ジェフリー・アレキサンダー |
| 本開示のいくつかの態様は確率的アナログデジタル変換器（ＡＤＣ）を提供する。 確率的ＡＤＣは、アナログ入力を可変長または可変振幅パルスに変換することと、そのパルスをスイッチングパルスとして複数のメモリ要素に印加することと、スイッチングパルスが印加された後に、値を記憶するメモリ要素の数に基づいてデジタル値を判断することとを行うように構成され得る。 | ||||||
| 7 | Accuracy enhancement techniques for ADCs | EP14186401.7 | 2014-09-25 | EP2858248A1 | 2015-04-08 | Shen, Junhua; Kapusta, Ronald A. |
Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.
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| 8 | Stochastic A/D converter and method for using the same | EP11173743.3 | 2011-07-13 | EP2546992B1 | 2014-03-05 | Verbruggen, Bob; Craninckx, Jan |
| 9 | Analog-to-digital converter | JP9357680 | 1980-07-09 | JPS5718124A | 1982-01-29 | YAMADA EISAKU |
| PURPOSE:To execute an A/D conversion whose temperature drift is small, by representing an output which has compared an input analog signal, and a pseudo random signal having amplitude whose probability density distribution is constant, by a pulse whose period is constant, and integrating it at every time of integer times of an external noise period. CONSTITUTION:An input analog signal f (t) is amplified at 1, and after that, is compared with a pseudo random signal P (t, x) 3. If an amplitude probability density function of the signal P is constant, the probability of f>P is in propeortion to (f). A pulse SP of a period Ts is generated 4, a comparison output 2 is represented, and is counted at 6. On the other hand, the pulse SP is frequency-divided at 7 into 1/N, is reset by a pulse Tc=NTs, a pulse having a period Tc is provided to a strobe terminal S of a latching circuit 8, too, a counting value is latched, and a digital output is obtained. In this regard, when this converter is used in a place where a periodical noise occurs, a noise can be removed by selecting Tc to integer times a period of a noise component. Since this converter has no RC circuit, it is free from a temperature drift, and a very small signal can be converted enough. | ||||||
| 10 | JPS5626176B2 - | JP3832976 | 1976-04-07 | JPS5626176B2 | 1981-06-17 | |
| 11 | Standard signal generator for ergodic converter | JP348977 | 1977-01-14 | JPS5287966A | 1977-07-22 | HERUMUUTO METSUTORAA |
| 12 | Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm | US15783107 | 2017-10-13 | US09966968B2 | 2018-05-08 | Raja Pullela; Curtis Ling |
| Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | ||||||
| 13 | SCALABLE STOCHASTIC SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER | US15282622 | 2016-09-30 | US20180097535A1 | 2018-04-05 | Eshel Gordon; Sophia Maerkovich; Ofir Degani; Hasnain Lakdawala |
| Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value. | ||||||
| 14 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM | US15783107 | 2017-10-13 | US20180054211A1 | 2018-02-22 | Raja Pullela; Curtis Ling |
| Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | ||||||
| 15 | Pixel information recovery by oversampling a comparison of pixel data and a noise signal | US15353936 | 2016-11-17 | US09866780B1 | 2018-01-09 | Denpol Kultran |
| An exemplary electronic light processing cell uses a photo sensor unit to provide an analog electrical output proportional to an amount of light impinging on the photo sensor. A noise source provides a noise output that is compared by a comparator, during a plurality of times during a frame of an image, with the analog electrical output to generate a binary digital output representative of each comparison. A digital counter counts the binary digital outputs during the frame and stores a count at the end of a frame where the value of the stored count is proportional the light impinging the photo sensor. The value of the stored count is adapted for use by an image processing unit to render an image. | ||||||
| 16 | STOCHASTIC ENCODING IN ANALOG TO DIGITAL CONVERSION | US14095690 | 2013-12-03 | US20150155878A1 | 2015-06-04 | Thomas M. MacLeod |
| A method and system for encoding an analog signal on a stochastic signal, the encoded signal then converted to a digital signal by an analog to digital converter, the analog to digital converter thereafter decoding from the encoded signal a digital signal, which corresponds to the analog signal. The stochastic signal may be a noise signal shaped to a Gaussian normal curve. An encoding process is performed by a multiplication circuit, which multiplies the stochastic signal by the analog signal, producing a product signal for an analog to digital conversion. During analog to digital conversion, the product signal is decoded. The decoding is performed using an arithmetic operation, which may be a Root Sum Square function or a Root Means Square function. The decoded signal is then mapped to account for offset error, gain error, and endpoint adjustment. The result is a decoded digital signal corresponding to the analog signal. | ||||||
| 17 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM | US14248851 | 2014-04-09 | US20140300499A1 | 2014-10-09 | Raja Pullela; Curtis Ling |
| Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | ||||||
| 18 | STOCHASTIC TIME-DIGITAL CONVERTER | US13983297 | 2012-05-29 | US20130307711A1 | 2013-11-21 | Jianhui Wu; Zixuan Wang; Xiao Shi; Meng Zhang; Cheng Huang; Chao Chen; Fuqing Huang; Xincun Ji; Ping Jiang |
| A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature. | ||||||
| 19 | SYSTEMS AND METHODS FOR DESIGNING ADC BASED ON PROBABILISTIC SWITCHING OF MEMORIES | US13238053 | 2011-09-21 | US20130069809A1 | 2013-03-21 | Subramaniam Venkatraman; Jeffrey Alexander Levin |
| Certain aspects of the present disclosure provide a probabilistic analog to digital converter (ADC). The probabilistic ADC may be configured to convert an analog input to a variable-length or variable-amplitude pulse, apply the pulse to a plurality of memory elements as a switching pulse, and determine a digital value based on a number of memory elements that store a value after the switching pulse is applied. | ||||||
| 20 | Analog-to-digital modulation | US11021140 | 2004-12-24 | US07224305B2 | 2007-05-29 | Jacobus C. Haartsen |
| A supplied analog signal is modulated by comparing the supplied analog signal with a noise signal. As a result of each comparison, an output signal is generated having a first value if the supplied analog signal is greater than the noise signal and generating an output signal having a second value if the supplied analog signal is lower than the noise signal. Such modulation is useful in applications such as analog-to-digital conversion. The transfer function of the modulator is a function of the distribution of the noise source. | ||||||
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