A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.

There is disclosed herein integrated circuitry, comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analogue converter circuitry.

Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC (500) can include a first SAR ADC (506) for each of a plurality of input channels (CH1, CH2,...,CHN), and a second SAR ADC (508), a multiplexer (510), and a residue amplifier (512) shared among the plurality of input channels. The multiplexer (510) can select an analog residue signal (Vres1,... ) from one of the first SAR ADCs (506) for conversion by the second SAR ADC (508). The residue amplifier (510) can amplify the selected analog residue signal (Vres1,...). The second SAR ADC (508), multiplexer (510), and/or residue amplifier (512) may be shared among all of the plurality of input channels (CH1,CH2, ...,CHN). Where the multichannel SAR ADC (600) includes N input channels, the second SAR ADC(608), multiplexer (610), and/or residue amplifier (612) may be shared among b channels of the N input channels.

The present disclosure relates to a method of self-calibration of a SAR-A/D converter, comprising a N_bit-bit digital-to-analog converter (DAC) for outputting a N_bit-bit output code, said digital-to-analog converter (DAC) comprising a first subconverter (C_MSB) having a plurality N_Th of thermometer elements T_j (1) and a second subconverter (C_LSB) having a plurality of binary-weighted elements N_Bin, said output code being defined by a thermometer scale S_Th having a number of levels equal to 2^NBitTh+1. The method is characterized in that it comprises the steps of:

- measuring, for each thermometer element of said plurality N_Th of thermometer elements T_j, an error value;

- determining a mean value (µ) of these values;

- dividing said plurality N_Th of thermometer elements T_j into a first subset (X) and a second subset (Y) each containing an identical number of values (x, y), equal to N_Th/2, wherein said first subset (X) comprises the thermometer elements T_j whose values are closer to said mean value (µ) as long as the error of the sum of thermometer elements T_j of the first subset (X) is not worse than the error value of the element farthest from said mean value (µ) of said first subset (X) and said second subset (Y) comprising all the remaining thermometer elements T_j;

- generating said thermometer scale, on the assumption that:

- each level m_i of said thermometer scale S_Th, with i ranging from 0 to N_Th/2, will be the incremental sum of each value (x) of said first ordered subset X;

- each further level m_i of said thermometer scale S_Th, with i ranging from N_Th/2+1 to N_Th, will be the sum of all the values (y) of said second subset Y plus the incremental sum of the elements (x) of the subset X in any order;

- generating said output code (OUTPUT) according to said thermometer scale S_Th.

The invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter (10) comprising

- precharging to a first state second terminals of capacitors (3) in each channel (1) of a plurality of channels and sampling (2) a reference analog input voltage signal (V_ref) applied via a first switchable path (6) whereby the sampled input voltage signal is received at first terminals of said capacitors,

- setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V_diff) at said first terminals,

- applying said reference analog input voltage signal to said first terminals via a second switchable path (7), said second path having a given impedance being higher than the known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal,

- quantizing said settling error, thereby obtaining an estimate of the non-zero settling error in each channel,

- comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch.

A multiplying digital-to-analog converter (MDAC) with capacitive load reset on an operational amplifier and a pipeline analog-to-digital converter using the MDAC are disclosed. The MDAC includes an operational amplifier and first and second switched-capacitor networks sharing the operational amplifier. The operational amplifier is further coupled with first capacitive load cells when the first switched-capacitor network is coupled to the operational amplifier, and the first capacitive load cells are reset when the first switched-capacitor network is disconnected from the operational amplifier. The operational amplifier is further coupled with second capacitive load cells when the second switched-capacitor network is coupled to the operational amplifier, and the second capacitive load cells are reset when the second switched-capacitor network is disconnected from the operational amplifier.

The present invention provides a method, a device and a system for processing data during idle listening. The method includes: sampling, in an idle listening mode, a first analog signal by using an N-bit ADC, and sampling, in a transceiving mode, a second analog signal by using an M-bit ADC, where N and M are both integers, and N is less than M. Embodiments of the present invention can reduce power consumption of an ADC during idle listening.

A calibration system for an analog-to-digital converter (ADC) comprising an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

The present disclosure describes an improved multi-stage noise shaping (MASH) analogto-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (Δ∑) modulator is provided at the front-end of the MASH ADC, and another full Δ∑ modulator is provided at the back-end of the MASH ADC. The front-end Δ∑ modulator digitizes an analog input signal, and the back-end Δ∑ modulator digitizes an error between the output of the front-end Δ∑ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.