A converter circuit provides analog to digital and digital to analog functions on a single silicon device. A flash analog to digital converter produces digital outputs using comparators which each receive an input signal and which each have different reference voltages. A decoder receiving digital inputs activates switches to connect selected ones of the same voltage references used by the flash analog to digital converter to a buffer which produces an analog output. The converter circuit can be a single or multi-stage flash analog to digital converter operating in a single channel or multi-channel environment. Timing and control logic prevents switching from occurring at times when perturbations on the voltage references could affect the analog and digital outputs.

In a codec having a coding section A/D converting an analog signal into a digital signal, and a decoding section D/A converting a received digital signal into an analog signal, a decoding timing generating circuit (50) is provided to generate a D/A conversion timing signal (S50) on the basis of a clock signal (S30b) generated by a coding PLL circuit (30) and a reading completion signal (S61a) supplied from decoding controller (61). In synchronism with this signal (S50), a D/A converter 62 converts the digital signal Di read by the decoding controller 61, into an analog signal, and sends it to the decoding filter 63. The decoding filter (63) operates synchronism with the clock signal (S30b) generated by the coding PLL circuit (30) to filter the output of the D/A converter (62), and outputs it as the analog signal (Ao). The S/N ratio due to asynchronous noises is improved, and the size, complexity, and the power consumption of the overall circuit are reduced, so the codec is suitable for implementation in an integrated circuit.

In a codec having a coding section A/D converting an analog signal into a digital signal, and a decoding section D/A converting a received digital signal into an analog signal, a decoding timing generating circuit (50) is provided to generate a D/A conversion timing signal (S50) on the basis of a clock signal (S30b) generated by a coding PLL circuit (30) and a reading completion signal (S61a) supplied from decoding controller (61). In synchronism with this signal (S50), a D/A converter 62 converts the digital signal Di read by the decoding controller 61, into an analog signal, and sends it to the decoding filter 63. The decoding filter (63) operates synchronism with the clock signal (S30b) generated by the coding PLL circuit (30) to filter the output of the D/A converter (62), and outputs it as the analog signal (Ao). The S/N ratio due to asynchronous noises is improved, and the size, complexity, and the power consumption of the overall circuit are reduced, so the codec is suitable for implementation in an integrated circuit.

In apparatus for processing an analog signal, a successive approximation ADC comprises a successive approximation register and a DAC. The final digital signal generated by the ADC is applied to digital processing equipment, such as a digital delay, and the output signal from the processing equipment is converted to analog form using the DAC of the ADC.

Der Erfindung liegt die Aufgabe zugrunde, den genannten Nullpunktabgleich so vorzunehmen, daß Langzeiteffekte berücksichtigt werden können. Erfindungsgemäß geschieht dies unter Verwendung eines an einen ersten Eingang des Vergleichers K angeschlossenen Nullabgleichkondensators CAZK, der zu Beginn der Abgleichphase, in der an beide Vergleichereingänge der Spannungswert Null gelegt ist, über ein Rückkopplungsnetzwerk RN mit den Vergleicherausgang in Verbindung gebracht wird, über das er in einen Ladungszustand versetzt wird, bei dem das Ausgangssignal des Vergleichers an der Entscheidungsschwelle zwischen den Gleichheit bzw. Ungleichheit der an den Vergleichereingängen anliegenden Analogwerten anzeigenden Ausgangssignalzuständen gelangt.