A system to convert between analog and digital signals, in some embodiments, comprises: a differentiator to produce a differentiated signal based on an input signal and a feedback signal; an integrator, coupled to the differentiator, to integrate the differentiated signal; a quantizer, coupled to the integrator, to quantize the integrated signal; and a low-pass feedback filter, coupled between an output of the quantizer and an input of the differentiator, to generate said feedback signal using the quantized signal, wherein the low-pass feedback filter pushes at least some noise of the quantized signal downward in the frequency spectrum.

Systems and methods for reducing spurious noise tones in sigma-delta analog-to-digital converters (ADCs) are described. A dither signal may be added to two differential input signals of a pseudo-differential sigma-delta ADC (400). The dither signal may be generated by a pseudo-random bit sequence generator (420) and applied to two input buffers (410), which add the dither signal to received differential analog input signals. The dithered signals may be digitized by two independent sigma-delta ADCs (120) and then subtracted (130) to remove the dither signal from an overall digital output signal (106).

A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.

A versatile detection circuit. A detection circuit optimized for low sensor voltages comprising a microprocessor (4), the microprocessor (4) comprising an integrated analog-to-digital converter (9) with an input pin, the integrated analog-to-digital converter (9) being configured to rely on a reference voltage of no more than 2 V, said detection circuit also comprising a transformation circuit for transforming a sensor (2, 102, 202, 302, 402) signal, said transformation circuit being connected to the input pin of the integrated analog-to-digital converter (9), characterised in that the transformation circuit may comprise an impedance converter (13) and with the exception of an impedance converter (13) relies only on passive electric elements (111, 112, 408, 409, 411, 412, 705, 706).

An absolute encoder includes a scale (2) in which a plurality of marks including a plurality of types of marks are arranged with a space and a period, a detector (3) including a plurality of elements arranged along a direction corresponding to the arrangement, and configured to detect a partial plurality of marks, and a signal processor (10) configured to perform quantization of an amplitude with respect to each period of periodic signals with a plurality of periods output from the detector to generate a data string, and generate, based on the data string, first position data having a resolution of the period. The signal processor is configured to obtain a plurality of thresholds for the quantization respectively corresponding to a plurality of periodic signals of the periodic signals with the plurality of periods based on a plurality of representative values respectively obtained from the periodic signals with the plurality of periods.

A calibration system for an analog-to-digital converter (ADC) comprising an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.