Method and circuit for bandwidth mismatch estimation in an a/d converter |
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申请号 | EP14171580.5 | 申请日 | 2014-06-06 | 公开(公告)号 | EP2953265A1 | 公开(公告)日 | 2015-12-09 |
申请人 | IMEC VZW; | 发明人 | Deguchi, Kazuaki; Verbruggen, Bob; Craninckx, Jan; | ||||
摘要 | The invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter (10) comprising - precharging to a first state second terminals of capacitors (3) in each channel (1) of a plurality of channels and sampling (2) a reference analog input voltage signal (V ref ) applied via a first switchable path (6) whereby the sampled input voltage signal is received at first terminals of said capacitors, - setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff ) at said first terminals, - applying said reference analog input voltage signal to said first terminals via a second switchable path (7), said second path having a given impedance being higher than the known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal, - quantizing said settling error, thereby obtaining an estimate of the non-zero settling error in each channel, - comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch. |
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权利要求 | |||||||
说明书全文 | The present invention is generally related to the field of high speed analogue-to-digital converters. In software defined radio an Analog-to-Digital converter (ADC) needs a speed of at least 200 MSamples/s and as much resolution as is feasible for a power budget of a few milliWatt, in order to simplify automatic gain control (AGC) and relax filtering requirements. In addition, since this ADC also needs to quantize much lower bandwidth standards, a dynamic solution is desirable. For such high speed ADCs interleaving is widely used. In high speed interleaved ADCs the effective ADC sampling frequency is increased by operating multiple ADCs alternately. Moreover, fully dynamic interleaved ADCs are of a special interest, as their total power consumption is independent of the number of parallel channels and the speed requirements for each individual channel are relaxed. However, interleaved ADCs suffer in general from mismatches among channels, gain mismatch and bandwidth mismatch. DC offset and gain mismatch are frequency-independent and can thus easily be calibrated in the digital domain. On the other hand, bandwidth mismatch due to capacitance and resistance mismatch in each sampling network of the interleaved ADC is frequency dependent and requires complex algorithms to be calibrated digitally. Consequently, spurious tones caused by bandwidth mismatch limit the high frequency input performance of interleaved ADCs. By applying correction for bandwidth mismatches in the sampling network bandwidths these spurs can be reduced. However, bandwidth errors first need to be estimated to determine how much correction, either in the digital or the analog domain, should be applied. Conventionally, in order to be able to observe bandwidth errors a high frequency input signal is required for generating errors due to bandwidth mismatch. In a background calibration scheme this high frequency input signal can be the signal to be quantized during normal operation. However, this requires certain assumptions about the nature of this input signal, some of which are not generally met. Additionally, applying a high frequency input requires an external signal generator, at the cost of valuable chip area and design time. Bandwidth mismatch calibration requires a practical way to detect bandwidth mismatch. While applying a high frequency sine wave to the ADC input and observing an output spectrum obviously allows for identification of bandwidth mismatch, this detection method requires both an external stimulus and quite a lot of computation in the FFT to obtain the ADC output spectrum. Patent In the paper " Alternatively, the paper " The solutions for bandwidth mismatch detection described in both above-mentioned papers however suffer from the drawback that significant additional analog circuits are required (analog signal conditioning and a redundant reference ADC, respectively) and that a significant amount of digital calculation is needed. They are thus not applicable in a low power design. Hence, there is a need for solutions for bandwidth mismatch in a time-interleaved A/D converter that are computationally simple and do not require additional hardware. It is an object of embodiments of the present invention to provide for a method for estimating bandwidth mismatch in a time-interleaved A/D converter and for a time-interleaved A/D converter adapted for applying said method, whereby no additional analog circuits are needed and only a moderate amount of calculation in the digital domain is required. The above objective is accomplished by the solution according to the present invention. In a first aspect the invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter comprising a plurality of channels, each channel comprising sampling means for sampling a reference analog input voltage signal, an array of capacitors connected in parallel and a quantizer arranged for converting the sampled input voltage at first terminals of the capacitors into a digital code. The method comprises
The proposed solution indeed allows for obtaining an estimated bandwidth mismatch based on the estimated settling errors. The bandwidth of each channel is determined by the capacitance value of the array of capacitors and the series impedance of the sampling means, both of which also affect the settling behaviour when the reference analog input is applied through the second switchable path. As a result, when the estimated settling error matches for all channels of the plurality of channels, it can be assumed that these channels also have a matching bandwidth. In a most preferred embodiment the second switchable path is in parallel to the first switchable path. In another aspect the invention relates to a time-interleaved analog-to-digital, A/D, converter arranged for receiving a reference analog input voltage signal and comprising a plurality of channels each comprising
characterised in that the reference analog input voltage signal can be applied to the sampling means of the plurality of channels via a first switchable path or via a second switchable path, said second path having a given impedance being higher than the impedance of the first path and in that the time-interleaved A/D converter comprises a control unit arranged for precharging second terminals of the capacitors of said plurality of channels to a first state, for switching in each channel the second terminals from the first state to a second state, for controlling the first and the second switchable path and for comparing estimates of non-zero settling errors of the channels and for deriving therefrom an estimation of the bandwidth mismatch. In a preferred embodiment the second switchable path is in parallel to the first switchable path. In a preferred embodiment the array of capacitors is part of a digital-to-analog converter (DAC). Many ADC architectures contain a DAC. In a preferred embodiment the time-interleaved A/D converter is implemented in a differential way. In one embodiment the second switchable path is connected between the differential inputs of the sampling means of the plurality of channels. In another embodiment each channel of said plurality comprises a first and a second Successive Approximation Register, SAR, whereby the second SAR has a higher resolution than the first SAR. For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. The above and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. The invention will now be described further, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments. Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated. In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. Bandwidth mismatch occurs due to mismatch in the on-resistance of the channel sampling switch and/or the capacitance value of the sampling capacitor, which causes amplitude and phase errors at high input frequencies. Designing the sampling network for intrinsic matching is complicated by the fact that the sampling capacitors are not necessarily located in close proximity in layout, meaning that typical foundry matching data is unreliable. In the proposed design this potential issue is avoided by adjusting the channel time constant. Channel bandwidth mismatch is detected using the proposed settling error detection method. A time-interleaved ADC 10 according to the present invention is illustrated in The detection of bandwidth mismatch according to this invention is based on settling error detection. It leverages the capacitive DAC array present in many ADC architectures for residue generation. As shown in In an embodiment each ADC channel 1 comprises a 6b coarse Successive Approximation register (SAR), a complementary dynamic residue amplifier A and a 10b fine SAR, as shown in the two-channel example of In a preferred embodiment a fully differential ADC implementation is adopted. In this embodiment both coarse and fine SAR are comparator-controlled to eliminate the need for a SAR controller by using 6 and 10 different comparators in coarse and fine stages, respectively. Both SARs are arranged to directly generate DAC feedback and asynchronously clock the next comparator in line as illustrated in The proposed estimation method will be now explained in details with reference to The series resistance in the second switchable path is required to ensure that a sufficiently large settling error is available for performing the quantization in step 4. The value of this resistance obviously also affects the size of the settling error, but since typically the same resistance is used for all channels, this is a common factor in all measurements. The period of time spent in step 3 should also be sufficiently short so that a sufficiently large settling error remains to be quantized. A detailed schematic of the operation of the differential sampling network is shown in An exemplary implementation of a controller and its waveforms for the time-interleaved ADC of When the counter is in the "00X" state and a rising edge arrives on channel<1>, the BWCal<1> signal is brought high. Similarly, if the counter is in "1XX" state and a rising edge arrives on channel<2> the BWCol<2> signal is brought high. These two signals ensure that the ADC channels are set to their appropriate states during the setup step of A simulation of the operation of this controller is shown in The variation of distortion as a result of bandwidth mismatch and the measured settling error as a function of the calibration setting of the channel switch are shown in In the embodiment shown in In the embodiments shown in In the embodiments described above, the second (high impedance) path is placed in parallel to the first path (low impedance) path. However, in a differential implementation, the second path may be connected in parallel to the input of the differential sampling means 2, as shown in While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. The invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope. |