METHOD AND APPARATUS FOR CONVERSION OF VOLTAGE VALUE TO DIGITAL WORD |
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申请号 | EP11779239.0 | 申请日 | 2011-06-05 | 公开(公告)号 | EP2577407B1 | 公开(公告)日 | 2017-08-09 |
申请人 | AKADEMIA GORNICZO-HUTNICZA im. Stanislawa Staszica; | 发明人 | KOSCIELNIK, Dariusz; MISKOWICZ, Marek; | ||||
摘要 | |||||||
权利要求 | |||||||
说明书全文 | The subject of this invention is a method and an apparatus for conversion of an voltage value to a digital word that can be applied in monitoring and control systems. The method for performing analog to digital conversion in a conversion circuit according to the document The method for analog to digital conversion according to the document The method for the conversion of the voltage signal to the digital signal known from the article ( The time-to-digital converter according to the document The apparatus for analog to digital conversion according to the document The apparatus for multi-channel analog to digital conversion according to the document The voltage analog-to-digital converter known from the article ( The accumulation of charge in the sampling capacitor and at the same time in the capacitor having the highest capacitance value in the array of capacitors allows the required capacitance value of the sampling capacitor to be reduced twice with the same maximum value of voltage obtained on the sampling capacitor. Moreover, it also allows the duration of the transfer of charge accumulated in the sampling capacitor to subsequent capacitors in the array to be decreased. Delivery of charge, which is accumulated in the sampling capacitor, or in the sampling capacitor and at the same time in the capacitor having the highest capacitance value in the array of capacitors, by the use of the current source allows the load of the source of the converted voltage to be constrained by the current source effectiveness. The use of two current sources whose effectivenesses are well chosen allows the conversion time to be limited while the required conversion accuracy may be guaranteed at the same time. The solution according to the invention is presented in the following figures:
The method according to the invention consists in that after detecting the beginning of the active state of the signal on the trigger input InS by means of the control module CM, the converted voltage value is mapped to the portion of electric charge proportional to this converted voltage value, and the portion of charge is accumulated in the sampling capacitor Cn by connecting the sampling capacitor Cn in parallel to the source of the converted voltage UIN during the active state of the signal on the trigger input InS, while the duration of the active state of the signal on the trigger input InS is not shorter than the assumed minimum value. After detecting the end of the active state of the signal on the trigger input InS by means of the control module CM, the function of the source capacitor Ci whose, index is defined by the content of the source capacitor Ci index register in the control module, CM is assigned by means of the control module CM to the sampling capacitor Cn by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register, and at the same time the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, is assigned by means of the control module CM to the capacitor Cn-1 having the highest capacitance value in the array A of capacitors while a capacitance value of each capacitor Cn-1, Cn-2, ..., C1, C0 of a given index is twice as high as a capacitance value of the capacitor of the previous index, by writing the value of the index of the capacitor Cn-1 to the destination capacitor Ck index register. Afterwards, the process of redistribution of the accumulated charge in capacitors Cn-1, Cn-2, ..., C1, C0 in the array A is realized during which charge accumulated in the source capacitor Ci is transferred to the destination capacitor Ck by the use of the current source I, and at the same time the voltage Uk increasing on the destination capacitor Ck is compared to the reference voltage UL value by the use of the second comparator K2, and also the voltage Ui on the source capacitor Ci is observed by the use of the first comparator K1. When the voltage Ui on the source capacitor Ci observed by the use of the first comparator K1 equals zero during the charge transfer, the function of the source capacitor Ci is assigned to the current destination capacitor Ck by means of the control module CM on the basis of the output signal of the first comparator K1 by writing the current content of the destination capacitor Ck index register in the control module CM to the source capacitor Ci index register in the control module CM, and also the function of the destination capacitor Ck is assigned to the subsequent capacitor in the array A whose capacitance value is twice lower than the capacitance value of the capacitor that operated as the destination capacitor directly before by reducing the content of the destination capacitor Ck index register by one, and charge transfer from a new source capacitor Ci to a new destination capacitor Ck is continued by the use of the current source I. When the voltage Uk on the destination capacitor Ck observed by the use of the second comparator K2 equals the reference voltage UL value during the transfer of charge from the source capacitor Ci to the destination capacitor Ck, the function of the destination capacitor Ck is assigned by means of the control module CM on the basis of the output signal of the second comparator K2 to the subsequent capacitor in the array A whose capacitance value is twice lower than the capacitance value of the capacitor that operated as the destination capacitor directly before by reducing the content of the destination capacitor Ck index register by one, and also the charge transfer from the source capacitor Ci to a new destination capacitor Ck is continued. This process is still controlled by means of the control module CM on the basis of the output signals of the comparators K1 and K2 until the voltage Ui on the source capacitor Ci observed by the use of the first comparator K1 equals zero during the period in which the function of the destination capacitor Ck is assigned to the capacitor Co having the lowest capacitance value in the array A of capacitors, or the voltage Uo increasing on the capacitor Co and observed at the same time by the use of the second comparator K2 equals the reference voltage UL value. The value one is assigned to these bits in the digital word, corresponding to the capacitors in the array A of capacitors, on which the voltage equal to the reference voltage UL value has been obtained, and the value zero is assigned to the other bits by means of the control module CM. In the another variant of the method, after detecting the beginning of the active state of the signal on the trigger input InS by means of the control module CM, electric charge is accumulated in the capacitor Cn-1 having the highest capacitance value in the array A of capacitors and at the same time in the sampling capacitor Cn connected in parallel to the capacitor Cn-1 in the array A of capacitors where the capacitance value of the sampling capacitor Cn is not smaller than the capacitance value of the capacitor Cn-1, by connecting at the same time both capacitors (Cn) and (Cn-1) in parallel to the source of the converted voltage UIN during the active state of the signal on the trigger input InS. After detecting the end of the active state of the signal on the trigger input InS by means of the control module CM, the function of the source capacitor Ci, whose index is defined by the content of the source capacitor Ci index register in the control module CM, is assigned by means of the control module CM to the sampling capacitor Cn by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register. At the same time, the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, is assigned by means of the control module CM to the capacitor Cn-1 having the highest capacitance value in the array A of capacitors by writing the value of the index of the capacitor Cn-1 to the destination capacitor Ck index register. After that the process of charge transfer from the source capacitor Ci to the destination capacitor Ck is realized by the use of the current source I. This process is controlled by means of the control module CM on the basis of the output signals of the comparators K1 and K2 until the voltage Ui on the current source capacitor Ci observed by the use of the first comparator K1 equals zero during the period in which the function of the destination capacitor Ck is assigned to the capacitor C0 having the lowest capacitance value in the array A of capacitors, or the voltage Uo, which increases on the capacitor C0 and is simultaneously observed by the use of the second comparator K2, equals the reference voltage UL value. In the another variant of the method, after detecting the beginning of the active state of the signal on the trigger input InS by means of the control module CM, electric charge is delivered by the use of the current source I and accumulated in the sampling capacitor Cn, and at the same time the voltage Un increasing on the sampling capacitor Cn is compared to the converted voltage UIN value by the use of the second comparator K2. This process is realized until the voltage Un, which increases on the sampling capacitor Cn equals the converted voltage UIN value. After that, the function of the source capacitor Ci whose index is defined by the content of the source capacitor Ci index register in the control module CM is assigned by means of the control module CM to the sampling capacitor Cn by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register. At the same time, the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, is assigned by means of the control module CM to the capacitor Cn-1 having the highest capacitance value in the array A of capacitors by writing the value of the index of the capacitor Cn-1 to the destination capacitor Ck index register. After that the process of electric charge transfer from the source capacitor Ci to the destination capacitor Ck is realized by the use of the current source I. This process is controlled by means of the control module CM on the basis of the output signals of the comparators K1 and K2 until the voltage Ui on the current source capacitor Ci observed by the use of the first comparator K1 equals zero during the period in which the function of the destination capacitor Ck is assigned to the capacitor C0 having the lowest capacitance value in the array A of capacitors, or the voltage Uo, which increases on the capacitor C0 and is simultaneously observed by the use of the second comparator K2, equals the reference voltage UL value. In the another variant of the method, after detecting the beginning of the active state of the signal on the trigger input InS by means of the control module CM, electric charge is delivered by the use of the current source I and accumulated in the capacitor Cn-1 having the highest capacitance value in the array A of capacitors and at the same time in the sampling capacitor Cn connected in parallel to the capacitor Cn-1 in the array A of capacitors where the capacitance value of the sampling capacitor Cn is not smaller than the capacitance value of the capacitor Cn-1, and at the same time the voltage Un increasing on the sampling capacitor Cn is compared to the converted voltage UIN value by the use of the second comparator K2. This process is realized until the voltage Un, which increases on the sampling capacitor Cn equals the converted voltage UIN value, and after that the function of the source capacitor Ci, whose index is defined by the content of the source capacitor Ci index register in the control module CM, is assigned by means of the control module CM to the sampling capacitor Cn by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register. At the same time, the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, is assigned by means of the control module CM to the capacitor Cn-1 having the highest capacitance value in the array A of capacitors by writing the value of the index of the capacitor Cn-1 to the destination capacitor Ck index register. After that, the process of charge transfer from the source capacitor Ci to the destination capacitor Ck is realized by the use of the current source I. This process is controlled by means of the control module CM on the basis of the output signals of the comparators K1 and K2 until the voltage Ui on the current source capacitor Ci observed by the use of the first comparator K1 equals zero during the period in which the function of the destination capacitor Ck is assigned to the capacitor C0 having the lowest capacitance value in the array A of capacitors, or the voltage U0, which increases on the capacitor C0 and is simultaneously observed by the use of the second comparator K2, equals the reference voltage UL value. In the another variant of the method, after detecting the beginning of the active state of the signal on the trigger input InS by means of the control module CM, electric charge is delivered by the use of the current source I and accumulated in the sampling capacitor Cn, and at the same time the voltage Un increasing on the sampling capacitor Cn is compared to the converted voltage UIN value by the use of the second comparator K2. This process is realized until the voltage Un, which increases on the sampling capacitor Cn equals the converted voltage UIN value. After that, the function of the source capacitor Ci, whose index is defined by the content of the source capacitor Ci index register in the control module CM, is assigned by means of the control module CM to the sampling capacitor Cn by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register. At the same time, the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, is assigned by means of the control module CM to the capacitor Cn-1 having the highest capacitance value in the array A of capacitors by writing the value of the index of the capacitor Cn-1 to the destination capacitor Ck index register. After that, the process of redistribution of accumulated charge is realized during which charge is transferred from the source capacitor Ci to the destination capacitor Ck by the use of the additional current source J whose effectiveness is different from the effectiveness of the current source I. The process of charge redistribution is controlled by means of the control module CM on the basis of the output signals of the comparators K1 and K2 until the voltage Ui on the current source capacitor Ci observed by the use of the first comparator K1 equals zero during the period in which the function of the destination capacitor Ck is assigned to the capacitor C0 having the lowest capacitance value in the array A of capacitors, or the voltage U0, which increases on the capacitor C0 and is simultaneously observed by the use of the second comparator K2, equals the reference voltage UL value. In the another variant of the method, after detecting the beginning of the active state of the signal on the trigger input InS by means of the control module CM, electric charge is delivered by the use of the current source I and accumulated in the capacitor Cn-1 having the highest capacitance value in the array A of capacitors and at the same time in the sampling capacitor Cn connected in parallel to the capacitor Cn-1 in the array A of capacitors where the capacitance value of the sampling capacitor Cn is not smaller than the capacitance value of the capacitor Cn-1, and at the same time the voltage Un increasing on the sampling capacitor Cn is compared to the converted voltage UIN value by the use of the second comparator K2. This process is realized until the voltage Un, which increases on the sampling capacitor Cn equals the converted voltage UIN value. After that, the function of the source capacitor Ci, whose index is defined by the content of the source capacitor Ci index register in the control module CM, is assigned by means of the control module CM to the sampling capacitor Cn by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register. At the same time, the function of the destination capacitor Ck whose index is defined by the content of the destination capacitor Ck index register in the control module CM, is assigned by means of the control module CM to the capacitor Cn-1 having the highest capacitance value in the array A of capacitors by writing the value of the index of the capacitor Cn-1 to the destination capacitor Ck index register. After that, the process of redistribution of accumulated charge is realized during which charge is transferred from the source capacitor Ci to the destination capacitor Ck by the use of the additional current source J whose effectiveness is different from the effectiveness of the current source I. The process of charge redistribution is controlled by means of the control module CM on the basis of the output signals of the comparators K1 and K2 until the voltage Ui on the current source capacitor Ci observed by the use of the first comparator K1 equals zero during the period in which the function of the destination capacitor Ck is assigned to the capacitor C0 having the lowest capacitance value in the array A of capacitors, or the voltage U0, which increases on the capacitor C0 and is simultaneously observed by the use of the second comparator K2, equals the reference voltage UL value. The apparatus according to the invention ( The array A in this variant of the apparatus ( In the another version of this apparatus variant ( In the another variant of the apparatus ( The array A in this variant of the apparatus ( In the another version of this apparatus variant ( In the another variant of the apparatus ( The array A in this variant of the apparatus ( In the another version of this apparatus variant ( The apparatus according to the invention operates as follows. Between successive cycles of conversion of voltage values to digital words having a number of bits equal to n, the control module CM keeps the apparatus in the state of relaxation during which the control module CM causes, by means of the control signals provided on the outputs In and In-1, In-2, ..., I1, I0, the closure of the first on-off switches SLn and SLn-1, SLn-2,..., SL1, SL0 and thereby the connection of the top plate of the sampling capacitor Cn and of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A to the first rail L, and also the switching of the change-over switches SGn, SGn-1,..., SG1, SG0 and thereby the connection of the bottom plate of the sampling capacitor Cn and also the connection of the bottom plates of the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A to the ground of the circuit. On the other hand, by means of the control signal provided on the output Dall, the control module CM causes the closure of the first rail on-off switch SGall and thereby the connection of the first rail L to the ground of the circuit enforcing in this way a complete discharge of the sampling capacitor Cn and of the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A. Afterwards, the control module CM causes, by means of the control signal provided on the output Dn-1, the closure of the second on-off switch SHn-1 and thereby the connection of the second rail H to the first rail L and to the ground of the circuit which prevents the occurrence of a random potential on the second rail H. At the same time, the control module CM causes, by means of the control signals provided on the output AU, the opening of the voltage source on-off switch SUn and thereby the disconnection of the top plate of the sampling capacitor Cn from the source of the converted voltage UIN. At the same time, the control module CM causes, by means of the control signals provided on the output Dn and on the outputs Dn-2, ..., D1, D0, the opening of the second on-off switches SHn and SHn-2, ..., SH1, SH0. At the same time, the control module CM causes, by means of the control signal provided on the output AI, the switching off the current source I ( When the control module CM detects the end of the active state of the signal on the trigger input InS of the apparatus, the control module CM causes, by means of the control signal provided on the output AU, the opening of the voltage source on-off switch SUn and thereby the disconnection of the top plate of the sampling capacitor Cn from the source of the converted voltage UIN. At the same time, the control module CM causes, by means of the control signal provided on the output In, the opening of the first on-off switch SLn and thereby the disconnection of the top plate of the sampling capacitor Cn from the first rail L, and also the concurrent switching of the change-over switch SGn and thereby the connection of the bottom plate of the sampling capacitor Cn to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output Dn-1, the opening of the second on-off switch SHn-1 and thereby the disconnection of the top plate of the capacitor Cn-1 from the second rail H. Next, by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register in the control module CM, the control module CM assigns the function of the source capacitor Ci, whose index is defined by the content of the source capacitor Ci index register, to the sampling capacitor Cn. At the same time, the control module CM causes, by means of the control signal provided on the output Di, the closure of the second on-off switch SHi and thereby the connection of the top plate of the source capacitor Ci to the second rail H. At the same time, by writing the value of the index of the capacitor Cn-1 having the highest capacitance value in the array A to the destination capacitor Ck index register in the control module CM, the control module CM assigns the function of the destination capacitor Ck whose index is defined by the content of the destination capacitor Ck index register to the capacitor Cn-1. Then, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. Then, by means of the control signal provided on the output AI, the control module CM causes the switching on the current source I by the use of which the charge accumulated in the source capacitor Ci is transferred through the second rail H and through the first rail L to the destination capacitor Ck ( In case when the voltage Uk on the current destination capacitor Ck reaches the reference voltage UL value during the charge transfer, the control module CM on the basis of the output signal of the second comparator K2 assigns the value one to the relevant bit bk in the digital word, and the control module CM causes, by means of the control signal provided on the output Ik, the opening of the first on-off switch SLk and thereby the disconnection of the top plate of the destination capacitor Ck from the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the source of auxiliary voltage UH. Afterwards, by reduction of the content of the destination capacitor Ck index register by one, the control module CM assigns the function of the destination capacitor Ck to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. After that, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of a new destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. In case when the voltage Ui on the source capacitor Ci reaches the value zero during the charge transfer, the control module CM, on the basis of the output signal of the first comparator K1 causes, by means of the control signal provided on the output Di, the opening of the second on-off switch SHi and thereby the disconnection of the top plate of the source capacitor Ci from the second rail H. At the same time, the control module CM causes, by means of the control signal provided on the output Ik, the opening of the first on-off switch SLk and thereby the disconnection of the top plate of the destination capacitor Ck from the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the source of auxiliary voltage UH. Next, the control module CM, on the basis of the output signal of the first comparator K1 by writing the current content of the destination capacitor Ck index register to the source capacitor Ci index register, assigns the function of the source capacitor Ci to the capacitor that until now has acted as the destination capacitor Ck, and after that the control module CM causes, by means of the control signal provided on the output Di, the closure of the second on-off switch SHi and thereby the connection of the top plate of a new source capacitor Ci to the second rail H. Afterwards, by reduction of the content of the destination capacitor Ck index register by one, the control module CM assigns the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. After that, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the new destination capacitor Ck to the ground of the circuit ( In both cases the control module CM continues to control the process of charge transfer on the basis of the output signals of both comparators K1 and K2. Each occurrence of the active state on the output of second comparator K2 causes the assignment of the function of the destination capacitor Ck to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. On the other hand, each occurrence of the active state on the output of first comparator K1 causes the assignment of the function of the source capacitor Ci to the capacitor that until now has acted as the destination capacitor Ck, and at the same time the assignment of the function of the destination capacitor Ck to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. The process of charge redistribution is terminated when the capacitor C0 having the lowest capacitance value in the array A stops to act as the destination capacitor Ck. Such situation occurs when the active state appears on the output of the first comparator K1 or on the output of the second comparator K2 during charge transfer to the capacitor C0. When the active state appears on the output of the second comparator K2, the control module CM assigns the value one to the bit b0. After termination of redistribution of charge accumulated previously in the sampling capacitor Cn and after assigning the corresponding values to the bits bn-1, bn-2, ..., b1, b0 in the output digital word, the control module CM activates the signal provided on the complete conversion signal output OutR and causes introduction of the apparatus into the relaxation phase by switching off the current source I, the opening of the voltage source on-off switch SUn and thereby the disconnection of the top plate of the sampling capacitor Cn from the source of the converted voltage UIN, also the closure of the first on-off switches SLn and SLn-1, SLn-2, ..., SL1, SL0 and thereby the connection of the top plate of the sampling capacitor Cn and the connection of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A to the first rail L, and also the concurrent switching of the change-over switches SGn and SGn-1, SGn-2, ..., SG1, SG0 to the positions connecting the bottom plate of the sampling capacitor Cn and the bottom plates of the capacitors Cn-1, Cn-2, ..., C1, C0 to the ground of the circuit. At the same time, the control module causes the closure of the first rail on-off switch SGall and thereby the connection of the first rail L to the ground of the circuit, enforcing a complete discharge of the sampling capacitor Cn and of the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A, and also the opening of the second on-off switches SHn and SHn-2, ..., SH1, SH0 in the array A, and also the closure of the second on-off switch SHn-1 and thereby the connection of the second rail H to the first rail L and to the ground of the circuit ( The operation of the another version of this apparatus variant consists in that during the time when the apparatus is kept in the state of relaxation, the control module CM causes, by means of the control signals provided on the output AU, the opening of the voltage source on-off switch SUn and thereby the disconnection of the top plate of the sampling capacitor Cn from the source of the converted voltage UIN, and also the opening of the additional voltage source on-off switch SUn-1 and thereby the disconnection of the top plate of the capacitor Cn-1 having the highest capacitance value in the array A from the source of the converted voltage UIN ( When the control module CM detects the end of the active state of the signal on the trigger input InS of the apparatus, the control module CM causes, by means of the control signal provided on the output AU, the opening of the voltage source on-off switch SUn and thereby the disconnection of the top plate of the sampling capacitor Cn from the source of the converted voltage UIN, and also the concurrent opening of the additional voltage source on-off switch SUn-1 and thereby the disconnection of the top plate of the capacitor Cn-1 from the source of the converted voltage UIN. At the same time, the control module CM causes by means of the control signal provided on the output In, the opening of the first on-off switch SLn and thereby the disconnection of the top plate of the sampling capacitor Cn from the first rail L, and also the concurrent switching of the change-over switch SGn and thereby the connection of the bottom plate of the sampling capacitor Cn to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output Dn-1, the opening of the second on-off switch SHn-1 and thereby the disconnection of the top plate of the capacitor Cn-1 from the second rail H. Next, by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register in the control module CM, the control module CM assigns the function of the source capacitor Ci, whose index is defined by the content of the source capacitor Ci index register, to the sampling capacitor Cn. At the same time, the control module CM causes, by means of the control signal provided on the output Di, the closure of the second on-off switch SHi, and thereby the connection of the top plate of the source capacitor Ci to the second rail H. At the same time, by writing the value of the index of the capacitor Cn-1 having the highest capacitance value in the array A to the destination capacitor Ck index register in the control module CM, the control module CM assigns the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register, to the capacitor Cn-1. Then, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. Then, by means of the control signal provided on the output AI, the control module CM causes the switching on the current source I by the use of which the charge accumulated in the source capacitor Ci is transferred through the second rail H and through the first rail L to the destination capacitor Ck. Next, the control module CM starts to control the process of redistribution of accumulated charge that is terminated when the capacitor Co having the lowest capacitance value in the array A stops to act as the destination capacitor Ck. After that the control module CM activates the signal provided on the complete conversion signal output OutR, and causes introducing the apparatus into the relaxation phase again. The another variant of the apparatus operates as follows. Between successive cycles of conversion of voltage values to digital words having a number of bits equal to n, the control module CM keeps the apparatus in the state of relaxation during which the control module CM causes, by means of the control signals provided on the outputs In and In-1,..., I1, I0, the closure of the first on-off switches SLn and SLn-1,..., SL1, SL0 and thereby the connection of the top plate of the sampling capacitor Cn and the connection of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A to the first rail L, and also the switching of the change-over switches SGn, SGn-1,..., SG1, SG0 and thereby the connection of the bottom plate of the sampling capacitor Cn and the connection of the bottom plates of the capacitors Cn-1, ..., C1, C0 in the array A to the ground of the circuit. On the other hand, by means of the control signal provided on the output Dall, the control module CM causes the closure of the first rail on-off switch SGall and thereby the connection of the first rail L to the ground of the circuit enforcing in this way a complete discharge of the sampling capacitor Cn and of the capacitors Cn-1, ..., C1, C0 in the array A. Afterwards, the control module CM causes, by means of the control signal provided on the output Dn-1, the closure of the second on-off switch SHn-1 and thereby the connection of the second rail H to the first rail L and to the ground of the circuit which prevents the occurrence of a random potential on the second rail H. At the same time, the control module CM causes, by means of the control signals provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the reference voltage UL. At the same time, the control module CM causes, by means of the control signals provided on the output Dn and on the outputs Dn-2, ..., D1, D0, the opening of the second on-off switches SHn and SHn-2, ..., SH1, SH0. At the same time, the control module CM causes, by means of the control signal provided on the output AI, the switching off the current source I, and on the other hand, by means of the control signal provided on the output AS, the switching of the current source change-over switch SI and thereby the connection of the one end of the current source I to the voltage supply UDD ( As soon as the control module CM detects the beginning of the active state of the signal on the trigger input InS of the apparatus, the control module CM causes, by means of the control signal provided on the output AU, the switching of the voltage source change-over switch SU and thereby the connection of the inverting input of the second comparator K2 to the source of the converted voltage UIN. At the same time, the control module CM causes, by means of the control signal provided on the output Dall, the opening of the first rail on-off switch SGall and thereby the disconnection of the first rail L from the ground of the circuit. At the same time, the control module CM causes, by means of the control signals provided on the outputs In-1, In-2, ..., I1, I0, the opening of the first on-off switches SLn-1, SLn-2,..., SL1, SL0 and thereby the disconnection of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A from the first rail L and also the switching of the change-over switches SGn-1, SGn-2, ..., SG1, SG0 and thereby the connection of the bottom plates of the capacitors Cn-1, Cn-2,..., C1, C0 to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output AI, the switching on the current source I ( When the voltage Un increasing on the sampling capacitor Cn reaches the converted voltage UIN value which represents the mapping of the converted voltage UIN value to the portion of electric charge proportional to this value and accumulated in the sampling capacitor Cn, the control module CM on the basis of the output signal of the second comparator K2 causes, by means of the control signal provided on the output In, the opening of the first on-off switch SLn and thereby the disconnection of the top plate of the sampling capacitor Cn from the first rail L, and also the concurrent switching of the change-over switch SGn and thereby the connection of the bottom plate of the sampling capacitor Cn to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output Dn-1, the opening of the second on-off switch SHn-1 and thereby the disconnection of the top plate of the capacitor Cn-1 from the second rail H. At the same time, the control module CM causes, by means of the control signals provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the reference voltage UL. Next, the control module CM causes, by means of the control signal provided on the output As, the switching of the current source change-over switch SI and thereby the connection of the one end of the current source I to the second rail H. Next, by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register in the control module CM, the control module CM assigns the function of the source capacitor Ci whose index is defined by the content of the source capacitor Ci index register to the sampling capacitor Cn. At the same time, the control module CM causes, by means of the control signal provided on the output Di, the closure of the second on-off switch SHi and thereby the connection of the top plate of the source capacitor Ci to the second rail H. At the same time, by writing the value of the index of the capacitor Cn-1 having the highest capacitance value in the array A to the destination capacitor Ck index register in the control module CM, the control module CM assigns the function of the destination capacitor Ck whose index is defined by the content of the destination capacitor Ck index register to the capacitor Cn-1. Then, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. Afterwards, the charge accumulated in the source capacitor Ci is transferred through the second rail H and through the first rail L to the destination capacitor Ck ( In case when the voltage Uk on the current destination capacitor Ck reaches the reference voltage UL value during the charge transfer, the control module CM on the basis of the output signal of the second comparator K2 assigns the value one to the relevant bit bk in the digital word, and the control module CM causes, by means of the control signal provided on the output Ik, the opening of the first on-off switch SLk and thereby the disconnection of the top plate of the destination capacitor Ck from the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the source of auxiliary voltage UH. Afterwards, by reduction of the content of the destination capacitor Ck index register by one, the control module CM assigns the function of the destination capacitor Ck to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. After that, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of a new destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. In case when the voltage Ui on the source capacitor Ci reaches the value zero during the charge transfer, the control module CM, on the basis of the output signal of the first comparator K1 causes, by means of the control signal provided on the output Di, the opening of the second on-off switch SHi and thereby the disconnection of the top plate of the source capacitor Ci from the second rail H. At the same time, the control module CM causes, by means of the control signal provided on the output Ik, the opening of the first on-off switch SLk and thereby the disconnection of the top plate of the destination capacitor Ck from the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the source of auxiliary voltage UH. Next, the control module CM, on the basis of the output signal of the first comparator K1 by writing the current content of the destination capacitor Ck index register to the source capacitor Ci index register, assigns the function of the source capacitor Ci to the capacitor that until now has acted as the destination capacitor Ck, and after that, the control module CM causes, by means of the control signal provided on the output Di, the closure of the second on-off switch SHi and thereby the connection of the top plate of a new source capacitor Ci to the second rail H. Afterwards, by reduction of the content of the destination capacitor Ck index register by one, the control module CM assigns the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. Then, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit ( In both cases, the control module CM continues to control the process of charge transfer on the basis of the output signals of both comparators K1 and K2. Each occurrence of the active state on the output of second comparator K2 causes the assignment of the function of the destination capacitor Ck to the subsequent capacitor in the array A, whose capacitance value is twice as lower as the capacitance value of the capacitor, which acted as the destination capacitor directly before. On the other hand, each occurrence of the active state on the output of first comparator K1 causes the assignment of the function of the source capacitor Ci to the capacitor that until now has acted as the destination capacitor Ck, and at the same time the assignment of the function of the destination capacitor Ck to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. The process of charge redistribution is terminated when the capacitor C0 having the lowest capacitance value in the array A stops to act as the destination capacitor Ck. Such situation occurs when the active state appears on the output of the first comparator K1 or on the output of the second comparator K2 during charge transfer to the capacitor C0. When the active state appears on the output of the second comparator K2, the control module CM assigns the value one to the bit b0. After termination of redistribution of charge delivered by the use of the current source I and accumulated previously in the sampling capacitor Cn and after assigning the corresponding values to the bits bn-1, bn-2, ..., b1, b0 in the output digital word, the control module CM activates the signal provided on the complete conversion signal output OutR and causes introduction of the apparatus into the relaxation phase by switching off the current source I, also the switching of the current source change-over switch SI and thereby the connection of the one end of the current source I to the voltage supply UDD, also the switching of the voltage source change-over switch SU to the position connecting the inverting input of the second comparator K2 to the source of the reference voltage UL, also the closure of the first on-off switches SLn and SLn-1, SLn-2, ..., SL1, SL0 and thereby the connection of the top plate of the sampling capacitor Cn and the connection of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A to the first rail L, and also the concurrent switching of the change-over switches SGn and SGn-1, SGn-2, ..., SG1, SG0 to the positions connecting the bottom plate of the sampling capacitor Cn and the bottom plates of the capacitors Cn-1, Cn-2, ..., C1, C0 to the ground of the circuit. At the same time, the control module causes the closure of the first rail on-off switch SGall and thereby the connection of the first rail L to the ground of the circuit, enforcing a complete discharge of the sampling capacitor Cn and of the capacitors Cn-1, Cn-2, ..., C1, C0 in the array A, and also the opening of the second on-off switches SHn and SHn-2, ..., SH1, SH0 in the array A, and also the closure of the second on-off switch SHn-1 and thereby the connection of the second rail H to the first rail L and to the ground of the circuit ( The operation of the another version of this apparatus variant consists in that as soon as the control module CM detects the beginning of the active state of the signal on the trigger input InS of the apparatus, the control module CM causes, by means of the control signal provided on the output AU, the switching of the voltage source change-over switch SU and thereby the connection of the inverting input of the second comparator K2 to the source of the converted voltage UIN. At the same time, the control module CM causes, by means of the control signal provided on the output Dall, the opening of the first rail on-off switch SGall and thereby the disconnection of the first rail L from the ground of the circuit. At the same time, the control module CM causes, by means of the control signals provided on the outputs In-2, ..., I1, I0, the opening of the first on-off switches SLn-2,..., SL1, SL0 and thereby the disconnection of the top plates of all the capacitors Cn-2, ..., C1, Co in the array A from the first rail L and also the switching of the change-over switches SGn-2, ..., SG1, SG0 and thereby the connection of the bottom plates of the capacitors Cn-2,..., C1, Co to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output AI, the switching on the current source I ( When the voltage Un increasing on the sampling capacitor Cn reaches the converted voltage UIN value, the control module CM on the basis of the output signal of the second comparator K2 causes, by means of the control signal provided on the output In, the opening of the first on-off switch SLn and thereby the disconnection of the top plate of the sampling capacitor Cn from the first rail L, and also the concurrent switching of the change-over switch SGn and thereby the connection of the bottom plate of the sampling capacitor Cn to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output Dn-1, the opening of the second on-off switch SHn-1 and thereby the disconnection of the top plate of the capacitor Cn-1 from the second rail H, and on the other hand, by means of the control signals provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the reference voltage UL. Next, the control module CM causes, by means of the control signal provided on the output As, the switching of the current source change-over switch SI and thereby the connection of the one end of the current source I to the second rail H. Next, by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register in the control module CM, the control module CM assigns the function of the source capacitor Ci whose index is defined by the content of the source capacitor Ci index register to the sampling capacitor Cn. At the same time, the control module CM causes, by means of the control signal provided on the output Di, the closure of the second on-off switch SHi and thereby the connection of the top plate of the source capacitor Ci to the second rail H. At the same time, by writing the value of the index of the capacitor Cn-1 having the highest capacitance value in the array A to the destination capacitor Ck index register in the control module CM, the control module CM assigns the function of the destination capacitor Ck whose index is defined by the content of the destination capacitor Ck index register to the capacitor Cn-1. Then, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. Afterwards, the charge accumulated in the source capacitor Ci is transferred through the second rail H and through the first rail L to the destination capacitor Ck ( The another variant of the apparatus operates as follows. Between successive cycles of conversion of voltage values to digital words having a number of bits equal to n, the control module CM keeps the apparatus in the state of relaxation during which the control module CM causes, by means of the control signals provided on the outputs In and In-1, In-2, ..., I1, I0, the closure of the first on-off switches SLn and SLn-1, SLn-2, ..., SL1, SL0 and thereby the connection of the top plate of the sampling capacitor Cn and the connection of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, Co in the array A to the first rail L, and also the switching of the change-over switches SGn and SGn-1,..., SG1, SG0 and thereby the connection of the bottom plate of the sampling capacitor Cn and the connection of the bottom plates of the capacitors Cn-1, ..., C1, Co in the array A to the ground of the circuit. On the other hand, by means of the control signal provided on the output Dall, the control module CM causes the closure of the first rail on-off switch SGall and thereby the connection of the first rail L to the ground of the circuit enforcing in this way a complete discharge of the sampling capacitor Cn and of the capacitors Cn-1, ..., C1, Co in the array A. Afterwards, the control module CM causes, by means of the control signal provided on the output Dn, the closure of the second on-off switch SHn and thereby the connection of the second rail H to the first rail L and to the ground of the circuit which prevents the occurrence of a random potential on the second rail H. At the same time, the control module CM causes, by means of the control signals provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the reference voltage UL. At the same time, the control module CM causes, by means of the control signals provided on the output Dn-1, Dn-2, ..., D1, D0, the opening of the second on-off switches SHn-1, SHn-2, ..., SH1, SH0. At the same time, the control module CM causes, by means of the control signal provided on the output AI, the switching off the current source I, and on the other hand, by means of the control signal provided on the output AJ, the switching off the additional current source J ( As soon as the control module CM detects the beginning of the active state of the signal on the trigger input InS of the apparatus, the control module CM causes, by means of the control signal provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the converted voltage UIN. At the same time, the control module CM causes, by means of the control signal provided on the output Dall, the opening of the first rail on-off switch SGall and thereby the disconnection of the first rail L from the ground of the circuit. At the same time, the control module CM causes, by means of the control signals provided on the outputs In-1, In-2, ..., I1, I0, the opening of the first on-off switches SLn-1, SLn-2, ..., SL1, SL0 and thereby the disconnection of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, Co in the array A from the first rail L, and also the switching of the change-over switches SGn-1, SGn-2, ..., SG1, SG0 and thereby the connection of the bottom plates of the capacitors Cn-1, Cn-2, ..., C1, Co to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output AI, the switching on the current source I ( When the voltage Un increasing on the sampling capacitor Cn reaches the converted voltage UIN value which represents the mapping of the converted voltage UIN value to the portion of electric charge proportional to this value and accumulated in the sampling capacitor Cn, the control module CM on the basis of the output signal of the second comparator K2 causes, by means of the control signal provided on the output AI, the switching off the current source I, and also by means of the control signal provided on the output In, the opening of the first on-off switch SLn and thereby the disconnection of the top plate of the sampling capacitor Cn from the first rail L, and also the concurrent switching of the change-over switch SGn and thereby the connection of the bottom plate of the sampling capacitor Cn to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signals provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the reference voltage UL. Next, by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register in the control module CM, the control module CM assigns the function of the source capacitor Ci whose index is defined by the content of the source capacitor Ci index register to the sampling capacitor Cn. At the same time, by writing the value of the index of the capacitor Cn-1 having the highest capacitance value in the array A to the destination capacitor Ck index register in the control module CM, the control module CM assigns the function of the destination capacitor Ck whose index is defined by the content of the destination capacitor Ck index register to the capacitor Cn-1. Then, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. Next, the control module CM causes, by means of the control signal provided on the output AJ, the switching on the additional current source J by the use of which the charge accumulated in the source capacitor Ci is transferred through the second rail H and through the first rail L to the destination capacitor Ck ( In case when the voltage Uk on the current destination capacitor Ck reaches the reference voltage UL value during the charge transfer, the control module CM on the basis of the output signal of the second comparator K2 assigns the value one to the relevant bit bk in the digital word, and the control module CM causes, by means of the control signal provided on the output Ik, the opening of the first on-off switch SLk and thereby the disconnection of the top plate of the destination capacitor Ck from the first rail L and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the source of auxiliary voltage UH. Afterwards, by reduction of the content of the destination capacitor Ck index register by one, the control module CM assigns the function of the destination capacitor Ck to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. After that the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of a new destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. In case when the voltage Ui on the source capacitor Ci reaches the value zero during the charge transfer, the control module CM, on the basis of the output signal of the first comparator K1 causes, by means of the control signal provided on the output Di, the opening of the second on-off switch SHi and thereby the disconnection of the top plate of the source capacitor Ci from the second rail H. At the same time, the control module CM causes, by means of the control signal provided on the output Ik, the opening of the first on-off switch SLk and thereby the disconnection of the top plate of the destination capacitor Ck from the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the source of auxiliary voltage UH. Next, the control module CM, on the basis of the output signal of the first comparator K1, by writing the current content of the destination capacitor Ck index register to the source capacitor Ci index register, assigns the function of the source capacitor Ci to the capacitor that until now has acted as the destination capacitor Ck, and after that, the control module CM causes, by means of the control signal provided on the output Di, the closure of the second on-off switch SHi and thereby the connection of the top plate of a new source capacitor Ci to the second rail H. Afterwards, by reduction of the content of the destination capacitor Ck index register by one, the control module CM assigns the function of the destination capacitor Ck, whose index is defined by the content of the destination capacitor Ck index register in the control module CM, to the subsequent capacitor in the array A, whose capacitance value is twice as lower as the capacitance value of the capacitor, which acted as the destination capacitor directly before. After that, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the new destination capacitor Ck to the ground of the circuit ( In both cases the control module CM continues to control the process of charge transfer on the basis of the output signals of both comparators K1 and K2. Each occurrence of the active state on the output of second comparator K2 causes the assignment of the function of the destination capacitor Ck to the subsequent capacitor in the array A whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. On the other hand, each occurrence of the active state on the output of the first comparator K1 causes the assignment of the function of the source capacitor Ci to the capacitor that until now has acted as the destination capacitor Ck, and at the same time the assignment of the function of the destination capacitor Ck to the subsequent capacitor in the array A, whose capacitance value is twice as lower as the capacitance value of the capacitor which acted as the destination capacitor directly before. The process of charge redistribution is terminated when the capacitor Co having the lowest capacitance value in the array A stops to act as the destination capacitor Ck. Such situation occurs when the active state appears on the output of the first comparator K1, or on the output of the second comparator K2 during charge transfer to the capacitor Co. When the active state appears on the output of the second comparator K2, the control module CM assigns the value one to the bit b0. After termination of redistribution of charge delivered by the use of the current source I and accumulated previously in the sampling capacitor Cn and after assigning the corresponding values to the bits bn-1, bn-2, ..., b1, bo in the output digital word, the control module CM activates the signal provided on the complete conversion signal output OutR and causes introduction of the apparatus into the relaxation phase by switching off the additional current source J, also the switching of the voltage source change-over switch SU to the position connecting the inverting input of the second comparator K2 to the source of the reference voltage UL, also the closure of the first on-off switches SLn and SLn-1, SLn-2, ..., SL1, SL0 and thereby the connection of the top plate of the sampling capacitor Cn and the connection of the top plates of all the capacitors Cn-1, Cn-2, ..., C1, Co in the array A to the first rail L, and also the concurrent switching of the change-over switches SGn and SGn-1, SGn-2, ..., SG1, SG0 to the positions connecting the bottom plate of the sampling capacitor Cn and the bottom plates of the capacitors Cn-1, Cn-2, ..., C1, Co to the ground of the circuit. At the same time, the control module causes the closure of the first rail on-off switch SGall and thereby the connection of the first rail L to the ground of the circuit, enforcing a complete discharge of the sampling capacitor Cn and of the capacitors Cn-1, Cn-2, ..., C1, Co in the array A, and also the opening of the second on-off switches SHn-1, SHn-2, ..., SH1, SH0 in the array A, and also the closure of the second on-off switch SHn and thereby the connection of the second rail H to the first rail L and to the ground of the circuit ( The operation of the another version of this apparatus variant consists in that as soon as the control module CM detects the beginning of the active state of the signal on the trigger input InS of the apparatus, the control module CM causes, by means of the control signal provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the converted voltage UIN. At the same time, the control module CM causes, by means of the control signal provided on the output Dall, the opening of the first rail on-off switch SGall and thereby the disconnection of the first rail L from the ground of the circuit. At the same time, the control module CM causes, by means of the control signals provided on the outputs In-2, ..., I1, I0, the opening of the first on-off switches SLn-2,..., SL1, SL0 and thereby the disconnection of the top plates of all the capacitors Cn-2, ..., C1, Co in the array A from the first rail L and also the switching of the change-over switches SGn-2, ..., SG1, SG0 and thereby the connection of the bottom plates of the capacitors Cn-2,..., C1, Co to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signal provided on the output AI, the switching on the current source I ( When the voltage Un increasing on the sampling capacitor Cn reaches the converted voltage UIN value, the control module CM on the basis of the output signal of the second comparator K2 causes, by means of the control signal provided on the output AI, the switching off the current source I, and on the other hand, by means of the control signal provided on the output In, the opening of the first on-off switch SLn and thereby the disconnection of the top plate of the sampling capacitor Cn from the first rail L, and also the concurrent switching of the change-over switch SGn and thereby the connection of the bottom plate of the sampling capacitor Cn to the source of auxiliary voltage UH. At the same time, the control module CM causes, by means of the control signals provided on the output AU, the switching of the voltage source change-over switch Su and thereby the connection of the inverting input of the second comparator K2 to the source of the reference voltage UL. Next, by writing the value of the index of the sampling capacitor Cn to the source capacitor Ci index register in the control module CM, the control module CM assigns the function of the source capacitor Ci whose index is defined by the content of the source capacitor Ci index register to the sampling capacitor Cn. At the same time, by writing the value of the index of the capacitor Cn-1 having the highest capacitance value in the array A to the destination capacitor Ck index register in the control module CM, the control module CM assigns the function of the destination capacitor Ck whose index is defined by the content of the destination capacitor Ck index register to the capacitor Cn-1. Then, the control module CM causes, by means of the control signal provided on the output Ik, the closure of the first on-off switch SLk and thereby the connection of the top plate of the destination capacitor Ck to the first rail L, and also the concurrent switching of the change-over switch SGk and thereby the connection of the bottom plate of the destination capacitor Ck to the ground of the circuit. Next, the control module CM causes, by means of the control signal provided on the output AJ, the switching on the additional current source J by the use of which the charge is transferred from the source capacitor Ci through the second rail H and through the first rail L to the destination capacitor Ck (
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