| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | JPH05508528A - | JP51198592 | 1992-05-05 | JPH05508528A | 1993-11-25 | |
| 162 | Synchronizing system for digital transmission | JP10555391 | 1991-05-10 | JPH05102936A | 1993-04-23 | KAWADA SHINICHI; TSUCHINO KEIICHIRO; WADA HIROSHI; IIDA MASAHISA |
| PURPOSE: To provide a synchronizing system for a digital transmission system that never sacrifices some of ADPCM signals for synchronization and never requires to separately transmit any signal exclusive for synchronization. CONSTITUTION: A monitoring circuit 22 monitors the quantizing step size of an adaptive adverse quantizer contained in an ADPCM decoder 20 and then applies a detection signal to a synchronization detecting circuit 23 with the largest quantizing step size. The circuit 23 counts the number of maximum value detection signals within a prescribed time and compares this count value with the threshold value. When the former value is larger than the latter one, an asynchronizing state signal is applied to a phase control circuit 24 and then a synchronizing state signal is applied to the circuit 24 vice versa. The circuit 24 increases the delayed variable of a variable delay circuit 21 by a single bit cycle of an ADPCM signal with application of the asynchronizing state signal. Then the circuit 24 fixes the delayed variable of the circuit 21 with application of the synchronizing state signal respectively. COPYRIGHT: (C)1993,JPO&Japio | ||||||
| 163 | JPH0423453B2 - | JP24859887 | 1987-09-30 | JPH0423453B2 | 1992-04-22 | YAGI TOSHIHARU |
| 164 | Synchronization detecting method using path metric value and branch metric value of viterbi decoder | JP28694990 | 1990-10-24 | JPH03187621A | 1991-08-15 | JIYONNSEON NO |
| PURPOSE: To improve reliability by non-linearly mapping the difference between a minimum path metrics and a minimum branch metrics corresponding to the pass metrics, adding a series of map values, generating a series of sums, and comporting each sum with a threshold. CONSTITUTION: A difference between a minimum path metrics and a minimum branch metrics is found out by an adder 3 and a zero difference and a non-zero difference are mutually separated by a non-linear mapping device 4. The zero difference is mapped on a 1st set having codes '1' and the non-zero difference is mapped on a 2nd set different from the set in which all codes are '1'. An adder 5 generates a sum S d of respective mapped values and a judging device 6 compares the sum S d with 1st and 2nd thresholds and declares an asynchronous state when a sum S d exceeds a 1st threshold, and when the sum S d is smaller than a 2nd threshold, declares a synchronous state. Consequently, the synchronous state of the Viterbi decoder can be reliably detected. COPYRIGHT: (C)1991,JPO | ||||||
| 165 | Synchronizing detection method in error correction device, its equipment and synchronizing method using the equipment | JP12782888 | 1988-05-24 | JPH02168753A | 1990-06-28 | SHIMADA MICHIO |
| PURPOSE: To prevent a phase from being changed regardless of a correct phase by generating a synchronizing detection signal when a time interval from a reception time of a reception signal subject to error correction at first till a reception time of a reception signal subject to error correction by an error correction circuit is larger than a predetermined interval. CONSTITUTION: A reset signal is inputted from an input terminal 102 and fed 10 a delay circuit 105. The reset signal is brought into a zero level for a prescribed time only buffer overflow takes place thereby initializing the internal state of the error correction circuit. The delay circuit 105 counts number of machine clocks inputted from the input terminal 101 when the reset signal goes to 1 and outputs a level '1' when the count is larger than the predetermined count. Since the content of a correction counter is fed to an input terminal 103, the content of the correction counter after initializing is stored in a register 106. A subtracter 107 subtracts the value fed to the input terminal 103 from the count of the register 106 and gives the result to a comparator 108. Thus, whether or not the phase is correct is discriminated. COPYRIGHT: (C)1990,JPO&Japio | ||||||
| 166 | JPH0160977B2 - | JP12094282 | 1982-07-12 | JPH0160977B2 | 1989-12-26 | YASUDA YUTAKA; HIRATA YASUO; MURAKAMI SHUJI; NAKAMURA KATSUHIRO; FURUYA YUKITSUNA |
| 167 | Decoder | JP24859887 | 1987-09-30 | JPS6490621A | 1989-04-07 | YAGI TOSHIHARU |
| PURPOSE:To reduce a synchronizing lock time by deciding an output string of a dummy bit insertion circuit by the timing signal outputted synchronously with the inserted phase of the dummy bit for the frequency division phase of a circuit applying serial/parallel conversion to the output data string of a dummy bit insertion circuit. CONSTITUTION:The circuit 1 applies parallel/serial conversion to data strings DP1, DQ1 to input the data string D1 and its clock signal to the circuit 2. The circuit 2 receives a control signal CT to output timing signals T1, T2 and the data string D2 inserted at a prescribed phase by a dummy bit into the reception data. The circuit 3 outputs the data string DP2, a succeeding data string DQ2 and timing signals TP, TQ when the signal T2 is '1' and a Viterbi decoding circuit 4 outputs the decoded bit string B2. The circuit 5 receives the B2 to output the bit string P3. On the other hand, an exclusive OR circuit 7 receiving the signal P3 and a signal being the result of retarding (6) the signal DP2 outputs '1' to the counter 9 when the result of comparison is dissident and the signal delayed (8) the signal TP is fed to an error counter 9. The counted value is supplied to a controlcircuit 10 and the signal CT is outputted. | ||||||
| 168 | Synchronization system for digital information signal | JP6101386 | 1986-03-20 | JPS61262333A | 1986-11-20 | ROTTMANN DIETER; KLANK OTTO |
| 169 | Transmitting and receiving device of error correction code | JP6723784 | 1984-04-03 | JPS60210044A | 1985-10-22 | OOSHIMA GOROU; KATOU KOUTAROU |
| PURPOSE: To monitor the generating frequency of error correction pulses and to simplify the set of synchronization by applying scrambling to both data obtained before and after coding with a transmitter then descrambling both data obtained before and after decoding with a receiver respectively. CONSTITUTION: A transmission input data signal 100 of a transmitter of an error correction code transmitting/receiving device is added with the output of a scrambling circuit 1 by an adder 21 and supplied to a coder 2. The coder 2 performs the error correction coding. Then the output of the coder 2 is added with the output of the circuit 1 by an adder 22, and the output of the adder 22 is outputted to a transmission line 3 as a transmission output data signal 101. A reception input signal 102 fed from the line 3 is added with the output of a descrambling circuit 5 by an adder 23 and supplied to a decoder 4. The output of the decoder 4 is added with the output of the circuit 5 by an adder 24. Then a reception output data signal 103 is outputted. Then the synchronization timing of the circuit 5 is monitored by an error correction pulse fed from the decoder 4. COPYRIGHT: (C)1985,JPO&Japio | ||||||
| 170 | Synchronizing circuit of viterbi decoder | JP12094482 | 1982-07-12 | JPS5912650A | 1984-01-23 | YASUDA YUTAKA; HIRATA YASUO; NAKAMURA KATSUHIRO; FURUYA YUKITSUNA; MURAKAMI SHIYUUJI |
| PURPOSE:To attain the synchronism of a code word, by discriminating whether or not a path exists between states corresponding to the respective maximum metric discriminated at a different time. CONSTITUTION:A decoding signal is outputted from a terminal 101 when a signal to be decoded inputted to a terminal 100 is applied to a Viterbi decoder 200 through a phase shifter 10, and a path discriminating circuit 40 discriminates whether or not a path exists between the state having the maximum metric at the past point of time and the state having the maximum metric at other point of time including the present point of time. Its discriminating signal is supplied to an integrator 50, integrated and supplied to a threshold value circuit 50, and a discriminating signal is outputted. This discriminating signal is supplied to the phase shifter 10 as a phase amount control signal of the phase shifter 10. | ||||||
| 171 | Error controller | JP1862182 | 1982-02-08 | JPS58137051A | 1983-08-15 | NAKAMURA KATSUHIRO |
| PURPOSE:To correct a shift due to synchronizing error automatically, by taking the number of bits required for the restoration of self-synchronism to a value not exceeding one-bit length. CONSTITUTION:A code polynomial division circuit 3 inputs a bit train supplied from a gate circuit 5 and that supplied to a buffer register 2. Whether or not the bit pattern outputted in parallel from the circuit 3 is a prescribed bit pattern is discriminated and an out-of-synchronism detection signal is outputted in response to the result of discrimination at an out-of-synchronism detection circuit. The bit error of the bit train read out from the register 2 is corrected depending on the bit pattern outputted in parallel with the circuit 3 and the predetermined bit pattern, and the bit at the specific order predetermined of the bit train read out from the register 2 is inverted at a bit inverter 13 and outputted. | ||||||
| 172 | Error controller | JP7021781 | 1981-05-12 | JPS57185546A | 1982-11-15 | NAKAMURA KATSUHIRO; NISHIWAKI MITSUO |
| PURPOSE:To reduce the synchronism recovering time, by inverting a specific bit of a reception signal added with a redundant bit and correcting and processing an output bit operated at a code polynominal division circuit with an out-of- synchronism detecting signal. CONSTITUTION:A reception signal added with a redundant bit and in which a specific number of order of bit is inverted, is inputted to a bit inverting circuit 2 and the bit of the specific number of order is inverted with a control of a clock SCLK from a control pulse producing circuit 12. The output of the circuit 2 is inputted to a buffer register 3 and a code polynominal division circuit 4. The output of the buffer 3 is gated 7 through the presence/absence of an out of synchronism detecting signal 5, inputted to the circuit 4 and added with the output of the circuit 2 for processing. The output of the circuit 4 is inputted to a bit error location detecting circuit 13 and an out of synchronism detection circuit 10 through the correction at a correction circuit 9 with a signal 5. When the number of times where all the bits of the output of the circuit 9 are not zero is consecutive for a prescribed number of blocks, the circuit 10 makes the signal 5 to 1 and the correction is made at the circuit 9 and the error bit location detected at the circuit 13 is corrected at a correction circuit 14 for output. | ||||||
| 173 | エンコーダの信号処理装置、エンコーダ、信号処理方法及びプログラム | JP2016153817 | 2016-08-04 | JP2018021845A | 2018-02-08 | 近藤 洋平 |
| 【課題】エンコーダの出力信号の誤差を補正する際に、トルクコマンドに影響を与える加速度成分の変動を抑制すること。 【解決手段】被測定体の移動に応じてエンコーダ内で発生するアナログ量である元信号から一定時間間隔毎に位置データを検出するエンコーダの信号処理装置であって、エンコーダが発生する元信号の1周期内において、等間隔で取得された少なくとも3点以上の位置データの検出誤差に基づいて、エンコーダが発生する元信号に含まれる検出誤差の近似曲線を算出する近似曲線算出部と、近似曲線算出部によって算出された検出誤差の近似曲線に基づいて、任意の時刻における位置データの検出誤差の近似値を計算する近似誤差計算部と、近似誤差計算部によって計算された位置データの検出誤差の近似値に基づいて、任意の時刻における位置データの検出誤差を補正する位置データ補正部と、を備える。 【選択図】図1 |
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| 174 | Incremental redundancy transmission in Mimo communication system | JP2010128925 | 2010-06-04 | JP5204152B2 | 2013-06-05 | タマー・カドウス |
| For an incremental redundancy (IR) transmission in a MIMO system, a transmitter processes (e.g., encodes, partitions, interleaves, and modulates) a data packet based on a selected rate to obtain multiple data symbol blocks. The transmitter transmits one data symbol block at a time until a receiver correctly recovers the data packet or all blocks are transmitted. Whenever a data symbol block is received from the transmitter, the receiver detects a received symbol block to obtain a detected symbol block, processes (e.g., demodulates, deinterleaves, re-assembles, and decodes) all detected symbol blocks obtained for the data packet, and provides a decoded packet. If the decoded packet is in error, then the receiver repeats the processing when another data symbol block is received for the data packet. The receiver may also perform iterative detection and decoding on the received symbol blocks for the data packet multiple times to obtain the decoded packet. | ||||||
| 175 | Concurrent code checker and hardware efficient high speed i / o has a built-in self-test and debug features | JP2007037099 | 2007-01-19 | JP5174357B2 | 2013-04-03 | スル チンソン; チョイ フーン; アーン ギジュン |
| 176 | System and method for data recovery | JP2010257420 | 2010-11-18 | JP2011175721A | 2011-09-08 | MATHEW GEORGE; YANG SHAOHAU; XIA HAITEO; MILADINOVIC NENAD |
| <P>PROBLEM TO BE SOLVED: To provide a system and a method for recovering data. <P>SOLUTION: The system and the method are provided for identifying a reproducible location on a storage medium. An identification circuit includes a media defect detection circuit 112 and an anchor fixing circuit 114. The media defect detection circuit 112 can operate to identify a media defect, and the anchor fixing circuit 114 can operate to identify a location based on the criterion of the media defect. The location is reproducible. <P>COPYRIGHT: (C)2011,JPO&INPIT | ||||||
| 177 | Incremental redundancy transmission in Mimo communication system | JP2006526329 | 2004-09-09 | JP4741495B2 | 2011-08-03 | カドウス、タマー |
| For an incremental redundancy (IR) transmission in a MIMO system, a transmitter processes (e.g., encodes, partitions, interleaves, and modulates) a data packet based on a selected rate to obtain multiple data symbol blocks. The transmitter transmits one data symbol block at a time until a receiver correctly recovers the data packet or all blocks are transmitted. Whenever a data symbol block is received from the transmitter, the receiver detects a received symbol block to obtain a detected symbol block, processes (e.g., demodulates, deinterleaves, re-assembles, and decodes) all detected symbol blocks obtained for the data packet, and provides a decoded packet. If the decoded packet is in error, then the receiver repeats the processing when another data symbol block is received for the data packet. The receiver may also perform iterative detection and decoding on the received symbol blocks for the data packet multiple times to obtain the decoded packet. | ||||||
| 178 | Incremental redundancy transmission in mimo communication system | JP2010128925 | 2010-06-04 | JP2010252365A | 2010-11-04 | KADOUS TAMER |
| <P>PROBLEM TO BE SOLVED: To provide an incremental redundancy transmission in a MIMO system. <P>SOLUTION: A transmitter processes a data packet based on a selected rate to obtain multiple data symbol blocks. The transmitter transmits one data symbol block at a time until a receiver correctly recovers the data packet or all blocks are transmitted. Whenever a data symbol block is received from the transmitter, the receiver detects a received symbol block to obtain a detected symbol block, processes all the detected symbol blocks obtained for the data packet, and provides a decoded packet. If the decoded packet is in error, then the receiver repeats the processing when another data symbol block is received for the data packet. <P>COPYRIGHT: (C)2011,JPO&INPIT | ||||||
| 179 | Data writing device and storage system | JP2005276921 | 2005-09-22 | JP4290688B2 | 2009-07-08 | 秀導 水野; 淳 江角 |
| 180 | Compensation system of the phase shift of the turbo decoder | JP2007526486 | 2005-06-01 | JP2008502246A | 2008-01-24 | ゲラール，ブノワ; バーボ，ジャン−ピエール; バンストラシール，クリストフ; ブロシエ，ジャン−マルク |
| 本発明は、ターボ符号化変調送信器により送信される信号のターボ符号受信システムに関するもので、以下の特徴を持つ。 ：ソフトデマッパー（１）の出力は、ターボ復号器（２）に接続され、更に適応ロックループを有している。 この適応ロックループは以下の構成を有している。 ：測定生成器（３）の入力はターボ復号器の出力に接続され、結果の信頼性ベクトル（LLR
ｏｕｔ ）を受信し、前記ベクトルをワードビットの最低信頼地の平均に等しい信頼性測定（Ｍ（Ｉ））に変換し、位相シフト推定器（４）に送信する。 その出力は、ソフトデマッパーの上流側に配置され、位相値（φ）の入力信号を補正する位相補償器（５）に接続される。
【選択図】図３ |
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