Error controller |
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| 申请号 | JP7021781 | 申请日 | 1981-05-12 | 公开(公告)号 | JPS57185546A | 公开(公告)日 | 1982-11-15 |
| 申请人 | Nec Corp; | 发明人 | NAKAMURA KATSUHIRO; NISHIWAKI MITSUO; | ||||
| 摘要 | PURPOSE:To reduce the synchronism recovering time, by inverting a specific bit of a reception signal added with a redundant bit and correcting and processing an output bit operated at a code polynominal division circuit with an out-of- synchronism detecting signal. CONSTITUTION:A reception signal added with a redundant bit and in which a specific number of order of bit is inverted, is inputted to a bit inverting circuit 2 and the bit of the specific number of order is inverted with a control of a clock SCLK from a control pulse producing circuit 12. The output of the circuit 2 is inputted to a buffer register 3 and a code polynominal division circuit 4. The output of the buffer 3 is gated 7 through the presence/absence of an out of synchronism detecting signal 5, inputted to the circuit 4 and added with the output of the circuit 2 for processing. The output of the circuit 4 is inputted to a bit error location detecting circuit 13 and an out of synchronism detection circuit 10 through the correction at a correction circuit 9 with a signal 5. When the number of times where all the bits of the output of the circuit 9 are not zero is consecutive for a prescribed number of blocks, the circuit 10 makes the signal 5 to 1 and the correction is made at the circuit 9 and the error bit location detected at the circuit 13 is corrected at a correction circuit 14 for output. | ||||||
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| 说明书全文 | |||||||
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