| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | Method of clock recovery in a TMDS repeater | US10065004 | 2002-09-09 | US20040049592A1 | 2004-03-11 | Alexander Yurusov |
| A method of clock recovery in digital transmission systems based on a transition minimized differential scaling (TMDS) is described. Repeater based on the said method allows a TMDS transmission over long lines to a plurality of TMDS receivers without accumulating of phase distortions. | ||||||
| 102 | Data transfer method, block synchronizing signal detecting method, and reproducing apparatus | US10363908 | 2003-03-07 | US20030174781A1 | 2003-09-18 | Akira Itou; Toshihiko Hirose |
| There is provided a method of detecting a block sync signal in which a sync signal and code sequence can be distinguished from each other to recognize the head of a block composed of a plurality of code words at the time of data reading or reception. A sync word detector (10) is supplied with a window signal Sync_window generated based on a parity OK signal supplied from a parity check circuit (12) and indicating a period between the sync word included in signal read from the medium (1) and the ID information, and detects the sync word as to a bit string detected by a PRML Viterbi detector (6) with the use of the Sync_window signal. | ||||||
| 103 | Coding apparatus and decoding apparatus for transmission/storage of information | US09580430 | 2000-05-30 | US06493838B1 | 2002-12-10 | Yoshihiro Kikuchi; Toshiaki Watanabe; Kenshi Dachiku; Takeshi Chujoh; Takeshi Nagai |
| An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code. | ||||||
| 104 | Maximum likelihood detection method and information recording and reproducing apparatus | US771015 | 1996-12-20 | US6003153A | 1999-12-14 | Kaneyasu Shimoda |
| A maximum likelihood detection method detects a maximum likelihood path using trellis transitions when decoding a code string which is obtained by encoded data by a sliding block coding employing trellis-coded partial response (TCPR) technique. The maximum likelihood detection method includes the steps of (a) inputting the code string, and (b) detecting a maximum likelihood path with respect to the code string from state transition paths using a number of trellis transition states greater than a number of states of a state transition pattern of the sliding block code. | ||||||
| 105 | Synchronization method in Viterbi decoder | US916204 | 1997-08-22 | US5937016A | 1999-08-10 | Young-Bae Choi |
| A synchronization method in Viterbi decoder is disclosed. The synchronization method performs a fast and an effective synchronization by depuncturing and Viterbi-decoding transmitted convolutional codes punctured in a predetermined puncturing pattern assuming that a code rate is 5/6, comparing the calculated CBER to a high/low threshold value, determining a code rate group to which the code rate of the convolutional codes belong, and performing a code rate detecting process, a phase synchronization and a pattern synchronization. Therefore, when performing the Viterbi decoding, a fast and more effective synchronization can be performed with improved efficiency. | ||||||
| 106 | Method for coding and decoding a digital message | US814938 | 1997-03-10 | US5832002A | 1998-11-03 | Jan Endresen; Erik Carlson |
| The present invention relates to a method for coding and transmitting a digital message (c(x)) comprising a first number of information bits (a(x)) and a second number of control bits (b(x)), said message or code word being normally transmitted continuously, as well as a method for receiving and decoding such a digital message. In order to allow for a reliable block synchronization and error detection, there is according to the invention suggested a code format by which there is avoided the need to wait for a start of a block or message, and by which there is allowed verification before syncronization. | ||||||
| 107 | Method of and circuit for detecting synchronism in viterbi decoder | US675517 | 1996-06-27 | US5809044A | 1998-09-15 | Toshiya Todoroki |
| A branch value output circuit checks a preceding state to which a maximum path metric state determined in a Viterbi decoding process by a Viterbi decoder has transited, uses the maximum path metric state, and determines a branch value between transitions. A correlator determines a correlation in each interval between the branch value and soft-decided received data and outputs a correlative value representing the correlation in each interval. A synchronism/asynchronism determining circuit determines whether the received data are in a synchronous or asynchronous condition based on the correlative value in each interval. If the received data are determined to be in an asynchronous condition by the synchronism/asynchronism determining circuit, the synchronism/asynchronism determining circuit supplies a phase control signal to a phase converter. The phase converter changes the phase of the received data in response to the phase control signal. Therefore, it can be detected whether the soft-decided received data are in the synchronous or asynchronous condition, and if the received data are in the asynchronous condition, the received data are controlled into the synchronous condition. | ||||||
| 108 | Device for synchronizing branches of a Viterbi decoder included in a multidimensional trellis coded digital data receiver | US530632 | 1995-09-20 | US5757834A | 1998-05-26 | Juing Fang; Mani Kimiavi |
| A branch synchronization device for multidimensional trellis coded digital data receivers using convolutional encoders includes a Viterbi decoder receiving two streams of symbols and supplying coded sequences and a time shifter for time shifting the symbol streams fed to the Viterbi decoder. The time shifter is controlled by a branch synchronization decision device generating a time shift control signal. The branch synchronization decision device cooperates with a calculator circuit receiving the coded sequences and supplying to the synchronization decision device an output signal of a first type if the coded sequences correspond to sequences such as would be obtained directly from the convolutional encoder and supplying an output signal of a second type if the coded sequences do not correspond to sequences that could have been obtained from the convolutional encoder. This output signal is fed to the branch synchronization device. | ||||||
| 109 | Optimization of synchronization control in concatenated decoders | US476433 | 1995-06-07 | US5710783A | 1998-01-20 | Daniel A. Luthi; Nadav Ben-Efraim |
| A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed video and audio signal transmitted from a direct broadcast satellite. Acquisition for three layers of synchronization are required, but once all three layers are in-sync, down stream data synchronization monitoring will suffice so that upstream synchronization monitoring can be disabled thus improving system robustness to noise bursts and false synchronization on false sync bytes generated at the transmission encoder during non-changing data signal conditions. | ||||||
| 110 | Method and apparatus for protecting data from mis-synchronization errors | US383201 | 1995-02-02 | US5528607A | 1996-06-18 | Lih-Jyh Weng; Bruce Leshay; Diana Langer |
| An encoder in a data processing system generates, from a single m-bit coset leader constant, or symbol, a coset leader, which is a series of k m-bit symbols that resembles a random sequence of km bits. The encoder encodes the m-bit initial coset leader constant in a linear feedback shift register that is characterized by a maximum length polynomial over GF(2). The constants are produced by the register at the same times as the error correction symbols are produced by the encoder. The corresponding constants and symbols are then XOR'd together before the symbols are concatenated with the data symbols to form a code word for recording. A decoder similarly generates the coset leader from the initial constant. The decoder XOR's these constants with the error correction symbols in a retrieved code word as part of a demodulation operation. If the head was in synchronism with the stored information during a read operation, XOR'ing the k coset leader constants with the error correction symbols of the retrieved code word removes the coset leader from these symbols, and thus, reproduces the original error correction symbols. Otherwise, the XOR operation combines the coset leader with a shifted version of itself and introduces into the retrieved code word a number of errors that exceeds the error correction capability of the error correction code used to encode the data. In the preferred embodiment, the linear feedback shift register is characterized by the maximum length polynomial X.sup.9 +X.sup.8 +X.sup.7 +X.sup.3 +X.sup.2 +1 over GF(2), and the m-bit initial coset leader constant is 100001011. | ||||||
| 111 | Synchronization arrangement for decoder-de-interleaver | US290321 | 1994-08-15 | US5519734A | 1996-05-21 | Nadav Ben-Efraim |
| A decoder/de-interleaver comprises a de-interleaver for de-interleaving received interleaved encoded data that includes periodic decoder synchronization signals to produce de-interleaved encoded data. A decoder decodes the de-interleaved encoded data to produce output data. The de-interleaver has a latency such that the de-interleaved encoded data is delayed by (B-1) times a period of the decoder synchronization signals plus a constant interval, where B is the interleave depth. A synchronization pulse generator receives the interleaved and encoded data and generates decoder synchronization pulses that are substantially coincident with the decoder synchronization signals. A delay unit is connected between the synchronization pulse generator and the decoder for delaying the decoder synchronization pulses by the constant interval. The decoder thereby receives decoder synchronization pulses that correspond to previous decoder synchronization signals, but functions properly because the relative timing is correct. The decoder has an error detecting function by which the first B-1 decoder synchronization pulses that are generated before the de-interleaver produces valid de-interleaved encoded data are ignored. | ||||||
| 112 | Dual mode radio communication unit | US973896 | 1992-11-10 | US5392300A | 1995-02-21 | David E. Borth; John R. Haug; Phillip D. Rasky; Gregory M. Chiasson |
| A dual mode radio communication unit for a digital communication system is provided having an error controller including an error detection encoder and a forward error correction encoder which encode an input information signal into an error protected data bit stream. In addition, the communication unit includes a mode selector which enables either the error detection encoder or the forward error correction encoder used with a particular mode of operation of the communication unit. Further, a corresponding dual mode radio communication unit is provided having an error controller for generating estimated information signal samples according to a group of algorithms consisting of either an error detection algorithm or an error correction algorithm. In addition, the corresponding communication unit includes a mode selector for receiving a signal according to a particular one of the group of algorithms which is associated with a particular mode of operation of the corresponding communication unit. | ||||||
| 113 | Synchronization system for use in digital transmission system | US879819 | 1992-05-07 | US5386436A | 1995-01-31 | Shinichi Kawada; Keiichiro Hijino; Hiroshi Wada; Masahisa Iida |
| In a synchronization system for use in a digital transmission system in which an encoded digital transmission signal at least part of bits of which have specific statistic characteristics is transmitted, a digital transmission signal received by a decoder within a digital transmission apparatus at a receiving end is subjected to a decoding processing in units of samples on the basis of a synchronous input signal. The digital transmission apparatus at the receiving end includes a monitor for monitoring internal states of the decoder which vary between a synchronous state and an asynchronous state owing to the statistic characteristics of the digital transmission signal, a synchronization detector for determining whether the digital transmission system is in the synchronous state based on an output of the monitor, and a phase shifter for shifting a relative phase of the digital transmission signal against a synchronous input signal supplied to the decoder, one bit by one on the digital transmission signal in units of samples, in the case that a determination result of the synchronization detector indicates the asynchronous state. | ||||||
| 114 | Method and apparatus for communicating interleaved data | US927827 | 1992-08-10 | US5241563A | 1993-08-31 | Woo H. Paik; John M. Fox; Scott A. Lery |
| An interleaver processes information in a pseudorandom order to provide pseudorandom interleaved data for communication to a deinterleaver. The pseudorandom interleaved data is processed at the deinterleaver in a pseudorandom order corresponding to that used at the interleaver means, to recover the original information. The pseudorandom processing at the deinterleaver is synchronized with the pseudorandom processing at the interleaver on a trial and error basis. In one embodiment, full synchronization occurs when a Viterbi decoder receiving data from the deinterleaver has a renormalization rate within a designated threshold and when enough synchronization words are detected in data output from the deinterleaver to meet a predetermined criterion. In another embodiment, a timer is used to initiate a new starting address for the pseudorandom processing at the deinterleaver during successive time intervals. Synchronization is achieved when a start address is found that results in the detection of enough synchronization words in data output from the deinterleaver to meet a predetermined synchronization criterion. | ||||||
| 115 | Error correction coding and decoding circuit for digitally coded information | US238838 | 1988-08-31 | US5003540A | 1991-03-26 | Koichi Yamazaki; Yasuyuki Kimura; Osamu Yamada; Toru Kuroda |
| An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of the circuit, a data load clock signal for loading data onto the circuit, and a data read clock signal for reading data from the circuit are delivered from an external circuit provided separately from the error correction coding and decoding circuit. | ||||||
| 116 | Frame synchronization | US55805 | 1987-05-29 | US4807230A | 1989-02-21 | Rangarajan Srinivasagopalan; James D. Pruett |
| Disclosed is a modem including a transmitter having a convolutional encoder for transforming each group interval digital data into an expanded bit sequence having symbol-selecting bits and subset-selecting bits forming a plurality of bit groups, with each bit group designating a 2-dimensional subset and the symbol-selecting bits being used to select one 2-dimensional symbol from each of the selected subsets, the transmitter further providing modulation of a carrier signal, and a receiver wherein synchronization of received frames of subset-selecting bits is provided by applying a parity check equation to a plurality of possible received frames of subset-selecting bits. | ||||||
| 117 | Linear feedback sequence detection with error correction | US903335 | 1986-09-03 | US4747105A | 1988-05-24 | Alan L. Wilson; Michael W. Bright; Eric F. Ziolko |
| A detector locates a shift register sequence within a digital data stream by correlating the data stream with a sequence generated locally from a portion of the data stream. Error correction circuitry estimates errors that may have corrupted the sequence during transmission across a noisy channel and corrects them to the extent possible. The data stream and local sequence are correlated during an interval that is shifted either ahead or behind the portion of the error-corrected data stream used to initialize the local sequence generator, thereby avoiding the region during which short-term correlation between the data stream and local sequence would otherwise cause false indications of detection when only noise or random data is being received. | ||||||
| 118 | Self-synchronizing interleaver for trellis encoder used in wireline modems | US707085 | 1985-03-01 | US4677626A | 1987-06-30 | William L. Betts; Kenneth Martinez |
| In the transmitter of a data communication system using QAM, a trellis coder with k-baud delay units is used for forward error correction. The output of the encoder is modulated using QAM to generate sequential baud signal elements. The redundant data bits generated are distributed among several non-consecutive bauds. At the receiver a plurality of distributed convolutional decoders are utilized to decode the received signal element. The distributed trellis decoder is self-synchronizing. | ||||||
| 119 | Digital communication system including an error correcting encoder/decoder and a scrambler/descrambler | US718725 | 1985-04-01 | US4639548A | 1987-01-27 | Goro Oshima; Kotaro Kato |
| An error correction code data communication system scrambles and descrambles both non-coded data and coded data by using substantially the same code process at the opposite ends of a transmission path. The frequency of the occurrence of an error correction pulse in a decoder is monitored to set up synchronization for descrambling. The transmitter includes an encoder for adding a correction code to a data signal to be transmitted, and a scrambler for randomizing the data signal. The receiver includes a descrambler for descrambling the data signal which was randomized by the scrambler, and a decoder for correcting a code error responsive to the error correction code. The scrambler modulo 2 adds an output of a random signal generator to both an input data signal and an output data signal. The descrambler modulo 2 adds an output of a second random signal generator to both an input data signal and an output data signal. | ||||||
| 120 | Frame synchronizing system in a receiver in a time-division multiplex transmission system | US747722 | 1985-06-21 | US4638478A | 1987-01-20 | Michinori Hatabe |
| In a receiver receiving a time-division multiplex signal of a plurality of channels with each channel signal having a start signal part, an address signal, an error detecting code signal part, an information signal part, and a blank interval arranged in this order, a channel detecting circuit for detecting the channel signal assigned to the receiver is provided with a blank interval detecting circuit in addition to an address detecting circuit, in order to avoid an erroneous detection of the address detection circuit at a start condition of the receiver. Application of the multiplex signal to the address detecting circuit is prevented until the blank interval detection circuit initially detects one blank interval of the multiplex signal. At a start condition of the receiver, application of the multiplex signal to the address detecting circuit starts not at an intermediate time position in one channel signal but at the start signal part of a subsequent channel signal. The channel detecting circuit is further provided with a circuit for detecting an incorrect synchronization condition by observing the error detecting code signal part. The incorrect synchronization detecting circuit, when detecting the incorrectly synchronized condition, resets the blank interval detecting circuit into an initial condition, so that the acquisition operation of the frame synchronization is carried out. Thus, the frame synchronization is established even if noise invades the multiplex signal as transmitted. | ||||||
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