Decoder |
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| 申请号 | JP24859887 | 申请日 | 1987-09-30 | 公开(公告)号 | JPS6490621A | 公开(公告)日 | 1989-04-07 |
| 申请人 | Nec Corp; | 发明人 | YAGI TOSHIHARU; | ||||
| 摘要 | PURPOSE:To reduce a synchronizing lock time by deciding an output string of a dummy bit insertion circuit by the timing signal outputted synchronously with the inserted phase of the dummy bit for the frequency division phase of a circuit applying serial/parallel conversion to the output data string of a dummy bit insertion circuit. CONSTITUTION:The circuit 1 applies parallel/serial conversion to data strings DP1, DQ1 to input the data string D1 and its clock signal to the circuit 2. The circuit 2 receives a control signal CT to output timing signals T1, T2 and the data string D2 inserted at a prescribed phase by a dummy bit into the reception data. The circuit 3 outputs the data string DP2, a succeeding data string DQ2 and timing signals TP, TQ when the signal T2 is '1' and a Viterbi decoding circuit 4 outputs the decoded bit string B2. The circuit 5 receives the B2 to output the bit string P3. On the other hand, an exclusive OR circuit 7 receiving the signal P3 and a signal being the result of retarding (6) the signal DP2 outputs '1' to the counter 9 when the result of comparison is dissident and the signal delayed (8) the signal TP is fed to an error counter 9. The counted value is supplied to a controlcircuit 10 and the signal CT is outputted. | ||||||
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| 说明书全文 | |||||||
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