Synchronizing detection method in error correction device, its equipment and synchronizing method using the equipment专利检索- .基于误差编码或译码的同步用于传输的入H04L7/048 专利检索查询-专利查询网

Synchronizing detection method in error correction device, its equipment and synchronizing method using the equipment
申请号	JP12782888	申请日	1988-05-24	公开(公告)号	JPH02168753A	公开(公告)日	1990-06-28
申请人	Nec Corp;			发明人	SHIMADA MICHIO;
摘要	PURPOSE: To prevent a phase from being changed regardless of a correct phase by generating a synchronizing detection signal when a time interval from a reception time of a reception signal subject to error correction at first till a reception time of a reception signal subject to error correction by an error correction circuit is larger than a predetermined interval. CONSTITUTION: A reset signal is inputted from an input terminal 102 and fed 10 a delay circuit 105. The reset signal is brought into a zero level for a prescribed time only buffer overflow takes place thereby initializing the internal state of the error correction circuit. The delay circuit 105 counts number of machine clocks inputted from the input terminal 101 when the reset signal goes to 1 and outputs a level '1' when the count is larger than the predetermined count. Since the content of a correction counter is fed to an input terminal 103, the content of the correction counter after initializing is stored in a register 106. A subtracter 107 subtracts the value fed to the input terminal 103 from the count of the register 106 and gives the result to a comparator 108. Thus, whether or not the phase is correct is discriminated. COPYRIGHT: (C)1990,JPO&Japio
权利要求
说明书全文

Synchronizing detection method in error correction device, its equipment and synchronizing method using the equipment

该功能需要专业版企业版VIP权限，您可以：