Error controller |
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| 申请号 | JP1862182 | 申请日 | 1982-02-08 | 公开(公告)号 | JPS58137051A | 公开(公告)日 | 1983-08-15 |
| 申请人 | Nec Corp; | 发明人 | NAKAMURA KATSUHIRO; | ||||
| 摘要 | PURPOSE:To correct a shift due to synchronizing error automatically, by taking the number of bits required for the restoration of self-synchronism to a value not exceeding one-bit length. CONSTITUTION:A code polynomial division circuit 3 inputs a bit train supplied from a gate circuit 5 and that supplied to a buffer register 2. Whether or not the bit pattern outputted in parallel from the circuit 3 is a prescribed bit pattern is discriminated and an out-of-synchronism detection signal is outputted in response to the result of discrimination at an out-of-synchronism detection circuit. The bit error of the bit train read out from the register 2 is corrected depending on the bit pattern outputted in parallel with the circuit 3 and the predetermined bit pattern, and the bit at the specific order predetermined of the bit train read out from the register 2 is inverted at a bit inverter 13 and outputted. | ||||||
| 权利要求 | |||||||
| 说明书全文 | |||||||
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