| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | Digital signal processing circuit | JP4172687 | 1987-02-25 | JPS63209209A | 1988-08-30 | IWAMATSU MASAYUKI |
| PURPOSE: To minimize the influence of the converting error of an A/D conversion and to prevent the deterioration of S/N providing a means to attenuate to an A/D converted digital signal to the value in which the digital signal processing means is not overflown at the input side of a digital signal processing means. CONSTITUTION: The analog signal of a processing object is converted to a digital signal with an A/D converter 10. The digital signal is inputted through a signal line 11 equivalent to a digital signal supplying means to an attenuator 18 equivalent to a digital signal attenuating means and attenuated in a prescribed quantity digital way. After a prescribed digital signal processing is executed by a digital signal processing part 12 equivalent to the digital signal processing means, the attenuated digital signal is converted to an analog signal by a D/A converter 14 equivalent to a D/A converting means. The analog signal is outputted through an amplifier 19 equivalent to an analog amplifying means. Thus, the overflowing is prevented and the clip of an output waveform can be prevented. COPYRIGHT: (C)1988,JPO&Japio | ||||||
| 42 | Analog-to-digital converter | JP6548581 | 1981-04-30 | JPS57181226A | 1982-11-08 | NAKASHIMA MASAHIKO |
| PURPOSE:To reduce the chip area of a parallel A/D converter by obtaining the low-order digit bits by obtaining a local analog signal which corresponds to the high-order digits by 2<n> units of switches, and then finding a difference between a sampled value and the local analog signal. CONSTITUTION:A group of reference voltages and an analog signal are compared mutually by comparators 141-147. Detecting circuits 152-157 find two comparators which output a ''0'' and a ''1''. A detecting circuit 151 detects all the comparators 141-147 outputting ''1''s, and a detector 158 detects all the comparators 141-147 outputting ''0''s. Their detection signals are converted by an encoder 16 into digital signals, which are outputted to output terminals 17. According to those outputs, switches 121-128 operate to lead a prescribed voltage to an output terminal 11. | ||||||
| 43 | Sampling system | JP8383180 | 1980-06-20 | JPS5710528A | 1982-01-20 | ENDOU KENJIROU; KITAGAWA KAZUO; KIRA EIJI |
| PURPOSE:To perform optimum control for the sampling rate according to the slope of signals, by adding a slope detector. CONSTITUTION:An analog input signal applied to an input terminal 51 is inputted to a sampling circuit 52 and a slope detector 53. The sampling circuit 52 samples input signals every time when clock pulses are given from a clock oscillator 54 and outputs the sampled series to an output terminal 55. A slope detector 53 detects the slope of an input signal to the circuit 52 and outputs a signal having the level corresponding to the slope, and the output is given to the clock oscillator 54 as a control signal. The clock oscillator 54 consists of a VCO, and the oscillated frequency is controlled with the output of the slope detector 53 so that the interval of clock pulses applied to the circuit 52 is smaller with greater slope of the input signal. | ||||||
| 44 | JPS4843668A - | JP9726772 | 1972-09-29 | JPS4843668A | 1973-06-23 | WILLIAMS JR R B; LOSHBOUGH R C; DEITEMEYER S A |
| 45 | ANALOG-TO-DIGITAL CONVERTER | EP16207359.7 | 2016-12-29 | EP3343776A1 | 2018-07-04 | Zanikopoulos, Athon; Janssen, Erwin; Doris, Konstantinos |
An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.
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| 46 | MICROCOMPUTER FOR MICROPHONE | EP15876768 | 2015-11-17 | EP3244308A4 | 2018-01-17 | TAKEMOTO MAKOTO; KATO AKIHIRO |
| The objective of the present invention is to make it possible to execute each of a plurality of application programs without taking into account the addresses of the programs. A microcomputer (100) is provided with: a program memory (108) which stores a plurality of microphone programs executed by a digital signal processing circuit (104); an address control circuit (109) which controls addresses in the program memory; a program address register (110) which stores the addresses of the microphone programs; and a program size register (111) which stores the sizes of the microphone programs. The address control circuit (109) calculates the addresses in the program memory on the basis of the program address register (110) and the program size register (111). | ||||||
| 47 | MICROCOMPUTER FOR MICROPHONE | EP15876768.1 | 2015-11-17 | EP3244308A1 | 2017-11-15 | TAKEMOTO, Makoto; KATO, Akihiro |
The objective of the present invention is to make it possible to execute each of a plurality of application programs without taking into account the addresses of the programs. A microcomputer (100) is provided with: a program memory (108) which stores a plurality of microphone programs executed by a digital signal processing circuit (104); an address control circuit (109) which controls addresses in the program memory; a program address register (110) which stores the addresses of the microphone programs; and a program size register (111) which stores the sizes of the microphone programs. The address control circuit (109) calculates the addresses in the program memory on the basis of the program address register (110) and the program size register (111). |
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| 48 | RECEIVER CIRCUITS WITH FEEDFORWARD SIGNAL PATH | EP16167566.5 | 2016-04-28 | EP3240197A1 | 2017-11-01 | Bolatkale, Muhammed; Breems, Lucien Johannes |
A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.
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| 49 | MULTI-LEVEL PARALLEL SUPER-HIGH SPEED ADC AND DAC USING LOGARITHMIC COMPANDING LAW | EP13731648 | 2013-02-22 | EP2800276A4 | 2016-04-13 | CHEN QIXING; LUO QIYU |
| 50 | VERFAHREN ZUM VERSTÄRKEN EINES ZUR FAHRZEUGUMFELDDETEKTION GEEIGNETEN ECHOSIGNALS UND VORRICHTUNG ZUM DURCHFÜHREN DES VERFAHRENS | EP12743922.2 | 2012-07-17 | EP2756599B1 | 2016-02-24 | KARL, Matthias |
| 51 | Method of forming an audio processing system and structure therefor | EP14158201.5 | 2014-03-06 | EP2778837B1 | 2016-01-13 | Coenen, Ivo; de Jesus, Paulo |
| In one embodiment, an audio processing system includes a frequency control block that forms a system clock and a master audio clock. The frequency control block is configured to change a frequency of the system clock and change a relationship between the system clock and the master audio clock so that the frequency of the master audio clock remains substantially constant. | ||||||
| 52 | Continuous-time oversampling pipeline analog-to-digital converter | EP14157548.0 | 2014-03-03 | EP2779464A2 | 2014-09-17 | Shibata, Hajime |
A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
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| 53 | Method of forming an audio processing system and structure therefor | EP14158201.5 | 2014-03-06 | EP2778837A1 | 2014-09-17 | Coenen, Ivo; de Jesus, Paulo |
In one embodiment, an audio processing system includes a frequency control block that forms a system clock and a master audio clock. The frequency control block is configured to change a frequency of the system clock and change a relationship between the system clock and the master audio clock so that the frequency of the master audio clock remains substantially constant.
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| 54 | VERFAHREN ZUM VERSTÄRKEN EINES ZUR FAHRZEUGUMFELDDETEKTION GEEIGNETEN ECHOSIGNALS UND VORRICHTUNG ZUM DURCHFÜHREN DES VERFAHRENS | EP12743922.2 | 2012-07-17 | EP2756599A1 | 2014-07-23 | KARL, Matthias |
| The present invention relates to a method for amplifying an echo signal, wherein an analogue echo signal suitable for vehicle environment detection is amplified by means of an amplification based on the runtime of the echo signal, wherein the analogue echo signal is amplified by means of an amplifier having a plurality of outputs, each with different amplification and a downstream A/D converter with a time-variable reference voltage. At the same time, switching occurs between the different outputs of the amplifier at predefined switchover times and the reference voltage of the A/D converter varies time-wise between the switching times in such a manner that at the output of the A/D converter the echo signal is present with a runtime-dependent overall amplification, which has a predefined profile. | ||||||
| 55 | MULTI-LEVEL PARALLEL SUPER-HIGH SPEED ADC AND DAC USING LOGARITHMIC COMPANDING LAW | PCT/CN2013000173 | 2013-02-22 | WO2013097831A3 | 2013-08-29 | CHEN QIXING; LUO QIYU |
| The invention relates to multi-level parallel super-high-speed ADC and DAC using logarithmic companding law. With the help of a zero-voltage-drop voltage tracker switch, a zero-loss threshold switch assembly is provided. The quantized voltage of the A/D and D/A conversion can be obtained directly in the voltage-dividing resistor, thereby simplifying the conversion process and reducing conversion error. Thus, multi-level/multi-position parallel super-high-speed A/D and D/A conversion using logarithmic companding law can be achieved at a high conversion rate and a low error rate. | ||||||
| 56 | SYSTEMS AND METHODS FOR NOISE CANCELING | PCT/US2014050787 | 2014-08-12 | WO2015023707A9 | 2015-04-16 | MORTENSEN MIKAEL; NGUYEN KHIEM QUANG; NOLET MELISSA |
| Active Noise Cancellation (ANC) systems and methods that reduce latency to improve performance. In certain embodiments the systems sample a noise signal using a sample period to create a stream of digital signal data that is representative of the noise signal. A data transport layer carries the digital signal data to a signal processor. The transport layer temporally organizes the digital signal data to place the digital signal data within an initial phase of a sample period. The remaining phase of the sample period is set to a duration that allows the signal processor to process the digital signal data carried in the initial phase and to output the processed data during the same sample period. In this way, the processing of data occurs within one sample period and the latency is reduced and predictable. | ||||||
| 57 | Signal Processing Unit and Method for Time of Flight Measurement | US15727376 | 2017-10-06 | US20190107608A1 | 2019-04-11 | Paul Ta |
| A signal processing unit for time of flight measurement includes an oscillation module, a transmission module, a detection module, a multiplier, an analog-to-digital-converter and a processing module. The oscillation module provides m reference phases. The transmission module generates a set of light impulses based on a selection phase selected out of the m reference phases. The detection module receives a set of reflections of the set of light impulses and to generate a detector signal based on the set of reflections. The multiplier obtains a result of a multiplication of the detector signal by a comparison phase. The analog-to-digital-converter converts the result of the multiplier into a digital signal. The processing module determines the comparison phase or the selection phase and calculates an approximate phase difference between the set of generated light impulses and the set of received reflections based on the digital signal. | ||||||
| 58 | Method and apparatus to digitize pulse shapes from radiation detectors | US13731720 | 2012-12-31 | US10027340B1 | 2018-07-17 | Andrew Weisenberger; John E. McKisson; Hai Dong; Chris Cuevas; John McKisson; Wenze Xi |
| A field programmable gate array based multi-channel flash ADC unit combined with a high speed multi-lane data communications channel/Ethernet-like modular intercommunication providing a complete but easily expandable high-speed data acquisition system. This apparatus and method permits high-speed pulse-shape digitalization allowing position resolution imaging of particles having a range of energies and is scalable to achieve the efficient capture of coincident data from large electromagnetic detector arrays. | ||||||
| 59 | ANALOG-TO-DIGITAL CONVERTER | US15849856 | 2017-12-21 | US20180191365A1 | 2018-07-05 | Athon Zanikopoulos; Erwin Janssen; Konstantinos Doris |
| An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter. | ||||||
| 60 | Analog-to-digital converter | US15849856 | 2017-12-21 | US10014875B1 | 2018-07-03 | Athon Zanikopoulos; Erwin Janssen; Konstantinos Doris |
| An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter. | ||||||
