| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 81 | Apparatus and method for compensating output signal | US14966393 | 2015-12-11 | US09465400B2 | 2016-10-11 | Jung Yong Kim; Chul Seung Lee |
| An apparatus for compensating for an output signal may include: a regulator configured to convert power supplied from a power supply unit into a preset voltage; an input unit configured to be supplied with a voltage from the regulator and receive an external input signal; a control unit configured to be supplied with the voltage from the regulator, and transmit the input signal after preset signal processing; and an output unit configured to be supplied with power from the power supply unit and output the received input signal. The input unit may receive a supply voltage of the power supply unit and transmits the received supply voltage to the control unit, and the control unit may compensate for the input signal based on a preset reference supply voltage of the power supply unit and the received supply voltage. | ||||||
| 82 | Sensor system using multiple modes for analog to digital conversion | US15018127 | 2016-02-08 | US09455734B2 | 2016-09-27 | Wolfgang Scherr; Mario Motz; Christof Bodner; Laneesh Raghavan |
| A device for converting analog to digital is disclosed. The device includes a dual mode converter and a control unit. The dual mode converter has a coarse mode and a fine mode. The dual mode converter is configured to receive an input signal and convert the input signal to a digital output having a selected resolution. The control unit is coupled to the dual mode converter and is configured to operate the converter in the coarse mode until a coarse approximation is obtained and to operate the converter in the fine mode until a fine approximation is obtained having the selected resolution. The fine mode includes multi-bit incremental tracking. | ||||||
| 83 | METHODS AND APPARATUS FOR IN-PIXEL FILTERING IN FOCAL PLANE ARRAYS | US14850067 | 2015-09-10 | US20150381183A1 | 2015-12-31 | Kenneth I. SCHULTZ; Brian M. TYRRELL; Michael W. KELLY; Curtis B. COLONERO; Lawrence M. CANDELL; Daniel MOONEY |
| Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal. | ||||||
| 84 | Leakage-current abatement circuitry for memory arrays | US13777243 | 2013-02-26 | US09191022B2 | 2015-11-17 | Loren McLaury |
| In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices. | ||||||
| 85 | Traveling-wave based high-speed sampling systems | US14173812 | 2014-02-05 | US09191020B2 | 2015-11-17 | Ahmet Tekin; Ahmed Emira; Suat Utku Ay; Enver Cavus; Ahmed Mohieldin |
| Communications data interface sampling systems configured effectively with fully-symmetric dual-loop traveling wave oscillators providing high frequency evenly spaced multiple phases to represent analog-in-nature continuous signals as digital stream of samples with best approximation to the original signal. | ||||||
| 86 | Methods and apparatus for in-pixel filtering in focal plane arrays including apparatus and method for counting pulses representing an analog signal | US14073338 | 2013-11-06 | US09159446B2 | 2015-10-13 | Kenneth I. Schultz; Brian Tyrrell; Michael W. Kelly; Curtis Colonero; Lawrence M. Candell; Daniel Mooney |
| Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal. | ||||||
| 87 | TRAVELING-WAVE BASED HIGH-SPEED SAMPLING SYSTEMS | US14173812 | 2014-02-05 | US20150222287A1 | 2015-08-06 | Ahmet Tekin; Ahmed Emira; Suat Utku Ay; Enver Cavus; Ahmed Mohieldin |
| Communications data interface sampling systems configured effectively with fully-symmetric dual-loop traveling wave oscillators providing high frequency evenly spaced multiple phases to represent analog-in-nature continuous signals as digital stream of samples with best approximation to the original signal. | ||||||
| 88 | A/D conversion system | US14471418 | 2014-08-28 | US09071259B2 | 2015-06-30 | Tomohiro Nezuka |
| An input signal is quantized by a quantizer after being passed through plural loop filters. A last-stage loop filter is formed of an operational amplifier for generating an output signal, a sampling capacitor for sampling the input signal, an integrating capacitor for integrating the signal sampled by the capacitor and plural switches for switching over signal paths. A control circuit controls on/off states of the switches to discharge the sampling capacitor and the integrating capacitor and causes the loop filter to repeat a sampling operation and an integrating operation plural times. The control circuit lastly connects the sampling capacitor and the integrating capacitor to a state, which is opposite to the state of the integrating operation time and turns on a converting switch so that the A/D converter A/D-converts the output signal of the loop filter. | ||||||
| 89 | ANALOG-TO-DIGITAL CONVERTING DEVICE AND ANALOG-TO-DIGITAL CONVERTING METHOD | US14540041 | 2014-11-13 | US20150171877A1 | 2015-06-18 | Yen-Chuan Huang; Chih-Hong Lou; Chi-Yun Wang; Li-Han Hung; Min-Hua Wu |
| An analog-to-digital converting device includes: an integrator arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter arranged to generate the first analog feedback signal according to the digital output signal. | ||||||
| 90 | Analog-to-digital conversion apparatus and method capable of achieving fast settling | US14480651 | 2014-09-09 | US09041575B2 | 2015-05-26 | Yuan-Ching Lien |
| A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit. | ||||||
| 91 | A/D CONVERSION SYSTEM | US14471418 | 2014-08-28 | US20150084798A1 | 2015-03-26 | Tomohiro NEZUKA |
| An input signal is quantized by a quantizer after being passed through plural loop filters. A last-stage loop filter is formed of an operational amplifier for generating an output signal, a sampling capacitor for sampling the input signal, an integrating capacitor for integrating the signal sampled by the capacitor and plural switches for switching over signal paths. A control circuit controls on/off states of the switches to discharge the sampling capacitor and the integrating capacitor and causes the loop filter to repeat a sampling operation and an integrating operation plural times. The control circuit lastly connects the sampling capacitor and the integrating capacitor to a state, which is opposite to the state of the integrating operation time and turns on a converting switch so that the A/D converter A/D-converts the output signal of the loop filter. | ||||||
| 92 | CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER | US14524729 | 2014-10-27 | US20150042501A1 | 2015-02-12 | Hajime SHIBATA |
| A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. | ||||||
| 93 | ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD CAPABLE OF ACHIEVING FAST SETTLING | US14480651 | 2014-09-09 | US20140375489A1 | 2014-12-25 | Yuan-Ching Lien |
| A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit. | ||||||
| 94 | COMMUNICATION DEVICE USING POWER LINE COMMUNICATION AND FREQUENCY-DIVISION MULTIPLEXING ON A PILOT LINE, AND RELATED SYSTEMS | US14346938 | 2012-09-26 | US20140355698A1 | 2014-12-04 | Nicolas Morand |
| The invention relates to a communication device using power line communication provided in a first system coupled to a second system via a power cable comprising a pilot line having a first impedance, which encounters at least second and third impedances and through which a first analog signal passes in a first frequency band. The device is arranged so as to: i) generate, from a local digital signal, a second analog power line communication signal having frequencies included in a second frequency band that has minimal overlap with the first frequency band; ii) supply the second analog signal to the pilot line via a capacitive means and iii) extract, from the analog signals passing through the pilot line, each second analog signal in order to convert the latter into a digital signal to be processed by the system. | ||||||
| 95 | Continuous-time oversampling pipeline analog-to-digital converter | US13869454 | 2013-04-24 | US08896475B2 | 2014-11-25 | Hajime Shibata |
| A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. | ||||||
| 96 | Signal receiving device and electronic apparatus using the same | US13798133 | 2013-03-13 | US08884794B2 | 2014-11-11 | Tsung-Ping Wei; Chia-Hsin Chen |
| A signal receiving device and an electronic apparatus using the same are provided. The signal receiving device includes a signal conversion unit, a signal analysis unit, and an impedance unit. The signal conversion unit receives an analog input signal and converts the analog input signal into a digital input signal. The signal analysis unit receives the digital input signal and analyzes a signal characteristic thereof to generate an impedance adjustment signal. The impedance unit coupled to the signal analysis unit and a signal input terminal of the signal receiving device receives the impedance adjustment signal to dynamically adjust an input impedance of the signal input terminal. Thereby, the signal receiving device analyzes an input signal to dynamically adjust the input impedance of the signal receiving device, so as to maintain an amplitude gain of the input signal to be within a limited input range of the signal receiving device. | ||||||
| 97 | METHODS AND APPARATUS FOR IN-PIXEL FILTERING IN FOCAL PLANE ARRAYS | US14073338 | 2013-11-06 | US20140321600A1 | 2014-10-30 | KENNETH I. SCHULTZ; BRIAN TYRRELL; MICHAEL W. KELLY; CURTIS COLONERO; LAWRENCE M. CANDELL; DANIEL MOONEY |
| Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal. | ||||||
| 98 | Analog-to-digital conversion apparatus and method capable of achieving fast settling | US13911082 | 2013-06-06 | US08860599B1 | 2014-10-14 | Yuan-Ching Lien |
| A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit. | ||||||
| 99 | SECURED AUDIO CHANNEL FOR VOICE COMMUNICATION | US14109108 | 2013-12-17 | US20140172422A1 | 2014-06-19 | Yaron Hefetz |
| A security device for hindering data theft and data leaks via audio channel of a computer system is based on passing the audio signals through a coding vocoder that receives input audio signal from a computer and compressing the signal to a low bit-rate digital data indicative of human speech; and a decoding vocoder that decompress the digital data back to a secure audio signal. The data transfer of the protected audio channel is intentionally limited not to exceed the bit-rate needed to carry vocoder-compressed human speech which is well below the capabilities of unprotected audio channel. Both analog and digital audio ports may be protected. Hardware bit-rate limiter protect the system from software hacking. | ||||||
| 100 | CONFIGURATION SEQUENCE FOR PROGRAMMABLE LOGIC DEVICE | US13904861 | 2013-05-29 | US20140108628A1 | 2014-04-17 | Umesh Ananthiah; Tramie Tran; Jamie Freed |
| Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data. | ||||||
QQ群二维码
意见反馈
意见反馈