MULTI-LEVEL PARALLEL SUPER-HIGH SPEED ADC AND DAC USING LOGARITHMIC COMPANDING LAW |
|||||||
| 申请号 | PCT/CN2013000173 | 申请日 | 2013-02-22 | 公开(公告)号 | WO2013097831A3 | 公开(公告)日 | 2013-08-29 |
| 申请人 | CHEN QIXING; LUO QIYU; | 发明人 | CHEN QIXING; LUO QIYU; | ||||
| 摘要 | The invention relates to multi-level parallel super-high-speed ADC and DAC using logarithmic companding law. With the help of a zero-voltage-drop voltage tracker switch, a zero-loss threshold switch assembly is provided. The quantized voltage of the A/D and D/A conversion can be obtained directly in the voltage-dividing resistor, thereby simplifying the conversion process and reducing conversion error. Thus, multi-level/multi-position parallel super-high-speed A/D and D/A conversion using logarithmic companding law can be achieved at a high conversion rate and a low error rate. | ||||||
| 权利要求 | |||||||
| 说明书全文 | |||||||
QQ群二维码
意见反馈
意见反馈