| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Reconfigurable wideband sub-ranging analog-to-digital converter | US14858335 | 2015-09-18 | US09595974B1 | 2017-03-14 | Victoria T. Pereira; Lloyd F. Linder; Douglas A. Robl; Brandon R. Davis; Toshi Omori |
| A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including a first sample and hold circuit for sampling an input signal, a first ADC configured to generate a digital representation of the sampled input signal from the first sample and hold circuit, and a first digital-to-analog converter (DAC) responsive to the output of the first ADC and configured to generate an analog representation of the digital representation of the sampled input signal. A control processor is provided and configured to generate a digital control signal. A current control circuit is responsive to the digital control signal for generating an analog current control signal for selectively altering a characteristic of at least one of the first ADC and the first DAC. | ||||||
| 182 | RC LATTICE DELAY | US15182430 | 2016-06-14 | US20160373101A1 | 2016-12-22 | Yunzhi Dong; VICTOR KOZLOV; WENHUA W. YANG; TREVOR CLIFFORD CALDWELL; HAJIME SHIBATA |
| An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area. | ||||||
| 183 | Analog to Digital Converter with Internal Timer | US14710105 | 2015-05-12 | US20160336953A1 | 2016-11-17 | Vincent Quiquempoix; Alexandre Barreto |
| An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time | ||||||
| 184 | Analog to digital converter with internal timer | US14710105 | 2015-05-12 | US09496887B1 | 2016-11-15 | Vincent Quiquempoix; Alexandre Barreto |
| An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time. | ||||||
| 185 | Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCS) | US14843445 | 2015-09-02 | US09413378B2 | 2016-08-09 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits. | ||||||
| 186 | METHOD AND APPARATUS FOR AUSCULTATING INAUDIBLE SIGNALS | US15021688 | 2014-09-07 | US20160224312A1 | 2016-08-04 | WEI WU |
| The prior auscultation technology is only applicable to the sound signals within the audio range and conducted by vibration. Disclosed in the present invention are a method and an apparatus for auscultating inaudible signals, and thus inaudible signals can be mapped into the audible range to form audible signals. The method comprises: obtaining signal data which comprise audible or inaudible signal data; extracting a signal waveform from the signal data; determining a play rate which allows the signal waveform to phonate by means of an audio play apparatus; and performing the auscultation with the signal waveform being played through the audio play apparatus at the play rate, or combining the play rate and the signal waveform to thereby constitute an audio signal, and then playing the audio signal through the audio player so as to achieve auscultation. When the method and apparatus of the present invention are applied, auscultation can be achieved on any physical parameter changes expressed by wave-shaped curve, which promises to extract information which would have been difficult to find within the inaudible signal in the prior art and promote the development of science and technology innovations. | ||||||
| 187 | APPARATUS AND METHOD FOR COMPENSATING OUTPUT SIGNAL | US14966393 | 2015-12-11 | US20160170434A1 | 2016-06-16 | Jung Yong KIM; Chul Seung LEE |
| An apparatus for compensating for an output signal may include: a regulator configured to convert power supplied from a power supply unit into a preset voltage; an input unit configured to be supplied with a voltage from the regulator and receive an external input signal; a control unit configured to be supplied with the voltage from the regulator, and transmit the input signal after preset signal processing; and an output unit configured to be supplied with power from the power supply unit and output the received input signal. The input unit may receive a supply voltage of the power supply unit and transmits the received supply voltage to the control unit, and the control unit may compensate for the input signal based on a preset reference supply voltage of the power supply unit and the received supply voltage. | ||||||
| 188 | Sensor system using multiple modes for analog to digital conversion | US14319177 | 2014-06-30 | US09258005B2 | 2016-02-09 | Mario Motz; Wolfgang Scherr; Christof Bodner; Leneesh Raghavan |
| A device for converting analog to digital is disclosed. The device includes a dual mode converter and a control unit. The dual mode converter has a coarse mode and a fine mode. The dual mode converter is configured to receive an input signal and convert the input signal to a digital output having a selected resolution. The control unit is coupled to the dual mode converter and is configured to operate the converter in the coarse mode until a coarse approximation is obtained and to operate the converter in the fine mode until a fine approximation is obtained having the selected resolution. The fine mode includes multi-bit incremental tracking. | ||||||
| 189 | Power supply noise cancelling circuit and power supply noise cancelling method | US14657728 | 2015-03-13 | US09240797B2 | 2016-01-19 | Kei Shiraishi; Masanori Furuta; Junya Matsuno; Tetsuro Itakura |
| According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal. | ||||||
| 190 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) | US14843445 | 2015-09-02 | US20150381196A1 | 2015-12-31 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits. | ||||||
| 191 | SENSOR SYSTEM USING MULTIPLE MODES FOR ANALOG TO DIGITAL CONVERSION | US14319177 | 2014-06-30 | US20150381194A1 | 2015-12-31 | Mario Motz; Wolfgang Scherr; Christof Bodner; Leneesh Raghavan |
| A device for converting analog to digital is disclosed. The device includes a dual mode converter and a control unit. The dual mode converter has a coarse mode and a fine mode. The dual mode converter is configured to receive an input signal and convert the input signal to a digital output having a selected resolution. The control unit is coupled to the dual mode converter and is configured to operate the converter in the coarse mode until a coarse approximation is obtained and to operate the converter in the fine mode until a fine approximation is obtained having the selected resolution. The fine mode includes multi-bit incremental tracking. | ||||||
| 192 | Analog-to-digital converting device and analog-to-digital converting method | US14540041 | 2014-11-13 | US09184754B2 | 2015-11-10 | Yen-Chuan Huang; Chih-Hong Lou; Chi-Yun Wang; Li-Han Hung; Min-Hua Wu |
| An analog-to-digital converting device includes: an integrator arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter arranged to generate the first analog feedback signal according to the digital output signal. | ||||||
| 193 | Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) | US14585656 | 2014-12-30 | US09136859B2 | 2015-09-15 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | ||||||
| 194 | Multi-stage parallel super-high-speed ADC and DAC of logarithmic companding law | US14366254 | 2013-02-22 | US09136852B2 | 2015-09-15 | Qixing Chen; Qiyu Luo |
| Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error. | ||||||
| 195 | Successive approximation analog-to-digital converter and method of analog-to-digital conversion | US14451080 | 2014-08-04 | US09106243B2 | 2015-08-11 | Choong-Hoon Lee; Michael Choi |
| An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. | ||||||
| 196 | Dynamic compression/decompression (CODEC) configuration | US14128004 | 2013-06-24 | US09083378B2 | 2015-07-14 | Zhonghui Jin; Nan Qiao |
| The present disclosure is directed dynamic compression/decompression (codec) configuration. In general, a device may include a codec configuration module to determine a configuration for use by the codec based on configuration criteria. The configuration criteria may include, for example, data characteristic information, system condition information and user expectation information. The configuration information may be used to select a codec configuration from one or more available codec configurations. For example, a benchmark module also in the device may determine the available codec configurations. After a codec configuration has been selected, it may be set in the codec. It may also be possible for the codec configuration module to monitor for changes in device operation (e.g., changes in the configuration criteria) and to update the codec configuration based on the monitored changes. | ||||||
| 197 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) | US14585656 | 2014-12-30 | US20150162928A1 | 2015-06-11 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | ||||||
| 198 | Method for amplifying an echo signal suitable for vehicle surroundings detection and device for carrying out the method | US14344117 | 2012-07-17 | US20150077135A1 | 2015-03-19 | Matthias Karl |
| A method for amplifying an echo signal, in which an analog echo signal suitable for detection of a vehicle's surroundings is amplified by a gain dependent on the transit time of the echo signal, the analog echo signal being amplified by an amplifier having a plurality of outputs, each having a different gain, and a downstream A/D converter having a time-variable reference voltage. In the process, there is a switch between the different outputs of the amplifier at predefined switching points in time, and the reference voltage of the A/D converter varies over time between the switching points in time in such a way that the echo signal is present at the output of the A/D converter with a transit time-dependent total gain having a predefined characteristic. | ||||||
| 199 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION | US14451080 | 2014-08-04 | US20150061904A1 | 2015-03-05 | Choong-Hoon LEE; Michael CHOI |
| An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. | ||||||
| 200 | Telescopic Amplifier with Improved Common Mode Settling | US14470682 | 2014-08-27 | US20150061767A1 | 2015-03-05 | Roswald Francis |
| Telescopic amplifier circuits are disclosed. In an embodiment, a telescopic amplifier includes an input stage for receiving differential input signals, an output stage for outputting differential output signals at the drains of a first output transistor and a second output transistor, a tail current transistor coupled to sources of a first input transistor and a second input transistor, a common mode feedback circuit coupled to the differential output signals and outputting a common mode output signal, and a circuit element coupled between the common mode output signal and a gate of the tail current transistor. In an embodiment the circuit element is a resistor. In another embodiment the circuit element is a source follower transistor. In additional embodiments a phase margin of the common mode feedback open loop gain of the amplifier is determined by the value of the resistor. Additional embodiments are disclosed. | ||||||
QQ群二维码
意见反馈
意见反馈