| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | Input path matching in pipelined continuous-time analog-to-digital converters | US15455971 | 2017-03-10 | US10084473B2 | 2018-09-25 | Venkatesh Srinivasan; Kun Shi; Victoria Wang; Nikolaus Klemmer |
| System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit. | ||||||
| 162 | Systems and methods for analog to digital conversion | US15684900 | 2017-08-23 | US10033395B1 | 2018-07-24 | Bruno Miguel Vaz |
| An analog to digital converter (ADC) circuit includes a first stage for converting a first analog voltage signal to a first digital signal including a first portion of a digital output signal representing the first analog voltage signal, and generate a first residue voltage based on the first analog voltage signal and the first digital signal. A first amplifier control unit generates a first amplifier start signal based on a second stage ready signal indicating that a second stage is ready to process a second analog voltage signal. In response to the second stage ready signal, a first amplifier generates the second analog voltage signal based on the first residue voltage. The second stage is configured to generate the second stage ready signal, receive the second analog voltage signal, and convert the second analog voltage signal to a second digital signal including a second portion of the digital output signal. | ||||||
| 163 | Capacitor circuit, circuit device, physical quantity detecting device, electronic apparatus, and moving object | US15862992 | 2018-01-05 | US10008333B2 | 2018-06-26 | Atsushi Tanaka; Hideo Haneda |
| A capacitor circuit includes: a capacitor array including a plurality of capacitors; a switch array including a plurality of switch circuits, the switch circuits being respectively connected to the capacitors of the capacitor array; a plurality of switch control signal lines supplied with a plurality of switch control signals; and a substrate having a major surface on which the switch circuits are formed. At least part of the capacitors of the capacitor array is formed of a first conductive layer. The switch control signal lines are formed of a second conductive layer provided between the major surface and the first conductive layer. The capacitor array and the switch array are disposed so as to overlap each other at least in part in a plan view when viewed in a normal direction of the major surface. | ||||||
| 164 | Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) | US15711177 | 2017-09-21 | US10003347B2 | 2018-06-19 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | ||||||
| 165 | Digital Modulator Entropy Source | US15691827 | 2017-08-31 | US20180123607A1 | 2018-05-03 | Abhijit Kumar Das; Brian Roger Elies |
| An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node. | ||||||
| 166 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, CMOS IMAGE SENSOR INCLUDING THE SAME AND OPERATING METHOD THEREOF | US15596014 | 2017-05-16 | US20180061881A1 | 2018-03-01 | Tae-Gyu KIM |
| A complementary metal oxide semiconductor (CMOS) image sensor includes a pixel array suitable for outputting a pixel signal corresponding to incident light; a row decoder suitable for selecting and controlling pixels in the pixel array by row lines; a tracking voltage generator suitable for generating a tracking voltage; a plurality of successive approximation register (SAR) analog-to-digital converters suitable for analog-to-digital converting a pixel signal by repeatedly performing N times (where N is a natural number representing desired resolution) a process of comparing the pixel signal generated by the pixel array with the tracking voltage generated by the tracking voltage generator and modulating the pixel signal; and a control unit suitable for controlling operations of the row decoder, the tracking voltage generator, and the plurality of SAR analog-to-digital converters. | ||||||
| 167 | ENCODER AND APPARATUS HAVING THE SAME | US15689904 | 2017-08-29 | US20180058885A1 | 2018-03-01 | Kousuke KUDO; Hitoshi NAKAMURA |
| An encoder includes a scale, a detector, and a processor. The processor executes a second process while executing a first process, calculates a first relative position of one of the scale and the detector to the other of the scale and the detector when a calculation of a relative position between them starts, and then calculates a second relative position of the one to the other based on a relative displacement amount between them and the first relative position. | ||||||
| 168 | Successive approximation register analog-to-digital converter, CMOS image sensor including the same and operating method thereof | US15596014 | 2017-05-16 | US09905603B1 | 2018-02-27 | Tae-Gyu Kim |
| A complementary metal oxide semiconductor (CMOS) image sensor includes a pixel array suitable for outputting a pixel signal corresponding to incident light; a row decoder suitable for selecting and controlling pixels in the pixel array by row lines; a tracking voltage generator suitable for generating a tracking voltage; a plurality of successive approximation register (SAR) analog-to-digital converters suitable for analog-to-digital converting a pixel signal by repeatedly performing N times (where N is a natural number representing desired resolution) a process of comparing the pixel signal generated by the pixel array with the tracking voltage generated by the tracking voltage generator and modulating the pixel signal; and a control unit suitable for controlling operations of the row decoder, the tracking voltage generator, and the plurality of SAR analog-to-digital converters. | ||||||
| 169 | Capacitor circuit, circuit device, physical quantity detecting device, electronic apparatus, and moving object | US15617292 | 2017-06-08 | US09892857B2 | 2018-02-13 | Atsushi Tanaka; Hideo Haneda |
| A capacitor circuit includes: a capacitor array including a plurality of capacitors; a switch array including a plurality of switch circuits, the switch circuits being respectively connected to the capacitors of the capacitor array; a plurality of switch control signal lines supplied with a plurality of switch control signals; and a substrate having a major surface on which the switch circuits are formed. At least part of the capacitors of the capacitor array is formed of a first conductive layer. The switch control signal lines are formed of a second conductive layer provided between the major surface and the first conductive layer. The capacitor array and the switch array are disposed so as to overlap each other at least in part in a plan view when viewed in a normal direction of the major surface. | ||||||
| 170 | LOW-NOISE CURRENT-IN CLASS D AMPLIFIER WITH SLEW RATE CONTROL MECHANISM | US15630942 | 2017-06-22 | US20180019758A1 | 2018-01-18 | Chuan-Hung Hsiao; Kuan-Ta Chen |
| A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate. | ||||||
| 171 | Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) | US15230735 | 2016-08-08 | US09800253B2 | 2017-10-24 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | ||||||
| 172 | CONTINUOUS TIME DELTA-SIGMA MODULATOR WITH A TIME INTERLEAVED QUANTIZATION FUNCTION | US15465305 | 2017-03-21 | US20170288693A1 | 2017-10-05 | Ashish Sharma Kumar; Rajeev Jain; Chandrajit Debnath |
| A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided. | ||||||
| 173 | Digital modulator entropy source | US15339931 | 2016-11-01 | US09780798B1 | 2017-10-03 | Abhijit Kumar Das; Brian Roger Elies |
| An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node. | ||||||
| 174 | RC lattice delay | US15182430 | 2016-06-14 | US09762221B2 | 2017-09-12 | Yunzhi Dong; Victor Kozlov; Wenhua W. Yang; Trevor Clifford Caldwell; Hajime Shibata |
| An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area. | ||||||
| 175 | Wideband analog to digital conversion by random or level crossing sampling | US15407981 | 2017-01-17 | US09729160B1 | 2017-08-08 | Farokh Marvasti; Mahdi Boloursaz Mashadi |
| Circuit and method for encoding an analog signal to a stream of bits at an Analog to Digital Converter (ADC) and subsequent reconstruction of the original signal from the bit stream at a Digital to Analog Converter (DAC), where the ADC module samples the analog signal at a sub-Nyquist rate and encodes the samples to a stream of bits. The bit steam is subsequently used to reconstruct the Nyquist-rate samples of the original analog signal at the DAC. The ADC samples the input signal in one of the two realizations of non-uniform sampling, namely, Random Sampling (RS) and Level Crossing (LC) sampling techniques, according to embodiments of the disclosed invention. | ||||||
| 176 | Method for amplifying an echo signal suitable for vehicle surroundings detection and device for carrying out the method | US14344117 | 2012-07-17 | US09698802B2 | 2017-07-04 | Matthias Karl |
| A method for amplifying an echo signal, in which an analog echo signal suitable for detection of a vehicle's surroundings is amplified by a gain dependent on the transit time of the echo signal, the analog echo signal being amplified by an amplifier having a plurality of outputs, each having a different gain, and a downstream A/D converter having a time-variable reference voltage. In the process, there is a switch between the different outputs of the amplifier at predefined switching points in time, and the reference voltage of the A/D converter varies over time between the switching points in time in such a way that the echo signal is present at the output of the A/D converter with a transit time-dependent total gain having a predefined characteristic. | ||||||
| 177 | INPUT PATH MATCHING IN PIPELINED CONTINUOUS-TIME ANALOG-TO-DIGITAL CONVERTERS | US15455971 | 2017-03-10 | US20170187387A1 | 2017-06-29 | Venkatesh Srinivasan; Kun Shi; Victoria Wang; Nikolaus Klemmer |
| System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit. | ||||||
| 178 | Communication device using power line communication and frequency-division multiplexing on a pilot line, and related systems | US14346938 | 2012-09-26 | US09692483B2 | 2017-06-27 | Nicolas Morand |
| The invention relates to a communication device using power line communication provided in a first system coupled to a second system via a power cable comprising a pilot line having a first impedance, which encounters at least second and third impedances and through which a first analog signal passes in a first frequency band. The device is arranged so as to: i) generate, from a local digital signal, a second analog power line communication signal having frequencies included in a second frequency band that has minimal overlap with the first frequency band; ii) supply the second analog signal to the pilot line via a capacitive means and iii) extract, from the analog signals passing through the pilot line, each second analog signal in order to convert the latter into a digital signal to be processed by the system. | ||||||
| 179 | Method for digital error correction for binary successive approximation analog-to-digital converter (ADC) | US15253348 | 2016-08-31 | US09667268B2 | 2017-05-30 | Francesca Girardi; Alberto Minuti; Germano Nicollini; Marco Zamprogno |
| An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons. | ||||||
| 180 | Input path matching in pipelined continuous-time analog-to-digital converters | US15068231 | 2016-03-11 | US09614510B2 | 2017-04-04 | Venkatesh Srinivasan; Kun Shi; Victoria Wang; Nikolaus Klemmer |
| System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit. | ||||||
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