| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) | US15711177 | 2017-09-21 | US20180013442A1 | 2018-01-11 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | ||||||
| 62 | Delta sigma modulator with dynamic error cancellation | US15489124 | 2017-04-17 | US09853657B2 | 2017-12-26 | Eeshan Miglani; Karthikeyan Gunasekaran; Santhosh Kumar Gowdhaman; Shagun Dusad |
| The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals. | ||||||
| 63 | System for conversion between analog domain and digital domain with mismatch error shaping | US15497240 | 2017-04-26 | US09831885B2 | 2017-11-28 | Yun-Shiang Shu |
| The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value. | ||||||
| 64 | RECEIVER CIRCUITS | US15481038 | 2017-04-06 | US20170317860A1 | 2017-11-02 | Muhammed Bolatkale; Lucien Johannes Breems |
| A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal. | ||||||
| 65 | Amplifier circuit | US15441075 | 2017-02-23 | US09806728B1 | 2017-10-31 | Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka |
| An amplifier circuit includes a sampling circuit and an amplifier connected to an output of the sampling circuit. A feedback capacitor is between an output terminal of the amplifier and an output terminal of the sampling circuit. A quantizer that includes a comparator is configured to quantize a voltage at the output terminal of the sampling circuit according to a comparison of a voltage at the output terminal of the sampling circuit to a voltage at the reference potential terminal of the comparator. The quantizer outputs a digital code according to the voltage comparison. A control circuit receives the digital code from the quantizer and stores the digital code in a register as a cancellation digital code. A digital-analog (D/A) converter outputs an analog signal in accordance with digital codes from the control circuit. | ||||||
| 66 | System for conversion between analog domain and digital domain with mismatch error shaping | US15246580 | 2016-08-25 | US09787316B2 | 2017-10-10 | Yun-Shiang Shu |
| The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value. | ||||||
| 67 | MICROCOMPUTER FOR MICROPHONE | US15508271 | 2015-11-17 | US20170288689A1 | 2017-10-05 | Makoto Takemoto; Akihiro Kato |
| The objective of the present invention is to make it possible to execute each of a plurality of application programs without taking into account the addresses of the programs. A microcomputer (100) is provided with: a program memory (108) which stores a plurality of microphone programs executed by a digital signal processing circuit (104); an address control circuit (109) which controls addresses in the program memory; a program address register (110) which stores the addresses of the microphone programs; and a program size register (111) which stores the sizes of the microphone programs. The address control circuit (109) calculates the addresses in the program memory on the basis of the program address register (110) and the program size register (111). | ||||||
| 68 | Continuous-time analog-to-digital converter | US15240278 | 2016-08-18 | US09774344B2 | 2017-09-26 | Hajime Shibata |
| A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. | ||||||
| 69 | SECURED AUDIO CHANNEL FOR VOICE COMMUNICATION | US15608790 | 2017-05-30 | US20170263261A1 | 2017-09-14 | Yaron Hefetz |
| A security device for hindering data theft and data leaks via audio channel of a computer system is based on passing the audio signals through a coding vocoder that receives input audio signal from a computer and compressing the signal to a low bit-rate digital data indicative of human speech; and a decoding vocoder that decompress the digital data back to a secure audio signal. The data transfer of the protected audio channel is intentionally limited not to exceed the bit-rate needed to carry vocoder-compressed human speech which is well below the capabilities of unprotected audio channel. Both analog and digital audio ports may be protected. Hardware bit-rate limiter protect the system from software hacking. | ||||||
| 70 | FINGERPRINT RECOGNIZING SENSOR WITH FAST RECOGNITION | US15602052 | 2017-05-22 | US20170255808A1 | 2017-09-07 | Jungkuo HSU |
| A fingerprint recognizing sensor with fast recognition, including: a substrate, a conductive plate, a passivation layer, a charging capacitor, a switch group, and an analog to digital (AD) converter; the conductive plate being arranged on the substrate; the passivation layer being arranged on the conductive pad for receiving a finger to detect a fingerprint; the switch group including a first switch and a second switch; the first switch controlling an input voltage to charge the charging capacitor; two ends of the second switch being electrically connected to the conductive plate and the first switch as well as the charging capacitor, respectively; the AD converter being electrically connected to the charging capacitor; where the second switch controls the charging capacitor to perform charge sharing for multiple times; and the AD converter outputs a fingerprint recognizing signal according to a residual voltage after the charge sharing. | ||||||
| 71 | Analog-to-digital converter with an increased resolution first stage | US15395285 | 2016-12-30 | US09735794B1 | 2017-08-15 | Sabu Paul; Raghu Nandan Srinivasa |
| One example includes a pipelined analog-to-digital converter device. The pipelined analog-to-digital converter device includes a capacitive digital-to-analog converter, a first analog-to-digital converter, and a second analog-to-digital converter. The capacitive digital-to-analog converter includes a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device while the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage. The second analog-to-digital converter is coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device. | ||||||
| 72 | SYSTEM FOR CONVERSION BETWEEN ANALOG DOMAIN AND DIGITAL DOMAIN WITH MISMATCH ERROR SHAPING | US15497240 | 2017-04-26 | US20170230056A1 | 2017-08-10 | Yun-Shiang Shu |
| The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value. | ||||||
| 73 | Configuration sequence for programmable logic device | US13904861 | 2013-05-29 | US09722612B2 | 2017-08-01 | Umesh Ananthiah; Tramie Tran; Jamie Freed |
| Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data. | ||||||
| 74 | Secured audio channel for voice communication | US14109108 | 2013-12-17 | US09697837B2 | 2017-07-04 | Yaron Hefetz |
| A security device for hindering data theft and data leaks via audio channel of a computer system is based on passing the audio signals through a coding vocoder that receives input audio signal from a computer and compressing the signal to a low bit-rate digital data indicative of human speech; and a decoding vocoder that decompress the digital data back to a secure audio signal. The data transfer of the protected audio channel is intentionally limited not to exceed the bit-rate needed to carry vocoder-compressed human speech which is well below the capabilities of unprotected audio channel. Both analog and digital audio ports may be protected. Hardware bit-rate limiter protect the system from software hacking. | ||||||
| 75 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) | US15230735 | 2016-08-08 | US20170134032A1 | 2017-05-11 | Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan |
| An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | ||||||
| 76 | DELTA SIGMA MODULATOR WITH DYNAMIC ERROR CANCELLATION | US15226436 | 2016-08-02 | US20170041019A1 | 2017-02-09 | Eeshan MIGLANI; Karthikeyan GUNASEKARAN; Santhosh Kumar GOWDHAMAN; Shagun DUSAD |
| The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals. | ||||||
| 77 | Leakage-current abatement circuitry for memory arrays | US14887210 | 2015-10-19 | US09542993B2 | 2017-01-10 | Loren McLaury |
| In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices. | ||||||
| 78 | METHOD FOR DIGITAL ERROR CORRECTION FOR BINARY SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) | US15253348 | 2016-08-31 | US20160373129A1 | 2016-12-22 | Francesca Girardi; Alberto Minuti; Germano Nicollini; Marco Zamprogno |
| An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons. | ||||||
| 79 | CONTINUOUS-TIME ANALOG-TO-DIGITAL CONVERTER | US15240278 | 2016-08-18 | US20160359498A1 | 2016-12-08 | HAJIME SHIBATA |
| A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. | ||||||
| 80 | Method for digital error correction for binary successive approximation analog-to-digital converter (ADC) | US14559178 | 2014-12-03 | US09473162B2 | 2016-10-18 | Francesca Girardi; Alberto Minuti; Germano Nicollini; Marco Zamprogno |
| An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons. | ||||||
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