A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplifed difference signal to a digital signal and summing the digital signal.

The present invention relates to analog-to-digital converters and more particularly to a delta-sigma analog-to-digital converter 1 for generating a digital signal as a function of an analog signal and a clock signal having a first phase and a second phase, said converter comprises:

- a first branch 11 for applying an analog input signal,

- a feedback branch for feeding back an analog reference signal, with a digital-to-analog converter 121,

- a loop filter 13,

- a quantizer 15, and

- a switch 16,



the switch being arranged and timely correlated with an output switch of said digital-to-analog converter in order to connect the input resistance and disconnect the digital-to-analog converter during said first phase and to disconnect the input resistance and connect the digital-to-analog converter during said second phase.

The present invention also relates to a method for operating the same.

A method of, and a converter for, converting an analogue input signal (X) to a digital output signal (Y) by incremental-delta conversion in which, at clock intervals, a non-uniform quantizer (7) produces digital quantizer signals, a digital-to-analogue converter (5) produces analogue quantizer signals that are a function of the digital quantizer signals, analogue difference signals (Q) are applied over a feedback loop to the quantizer (7) that are a function of the difference between the input signal (X) and the integral of the analogue quantizer signals since a reset signal, and the digital output signal (Y) is produced as a function of the sum of the digital quantizer signals since the reset signal. The digital quantizer signals have a first magnitude (q) if the magnitude of the analogue difference signals (Q) is less than a threshold magnitude (V_t) and a second magnitude (r), substantially greater than the first magnitude (q), if the magnitude (Q) of the analogue difference signals is greater than the threshold magnitude (V_t), the threshold magnitude (V_t) being substantially less than the magnitude (V_r) of the analogue quantizer signals corresponding to the second magnitude (r). The magnitude of the change in the analogue difference signals (Q) between two successive clock cycles is substantially less than the magnitude of the corresponding analogue quantizer signals (V_q, V_r), so that the gain (g) of the feedback loop from the digital-to-analogue converter (5) to the quantizer (7) is substantially less than one.

A circuit for processing the control signal inputs for a delta modulation digital audio decoder wherein a reference voltage and a reference current are generated to cancel out variations in temperature, resistance, process variations and circuit voltages to yield a stable control signal current.

A circuit for processing the control signal inputs for a delta modulation digital audio decoder wherein a reference voltage and a reference current are generated to cancel out variations in temperature, resistance, process variations and circuit voltages to yield a stable control signal current.

An embodiment of the invention relates to a method of phase detection in a receiver circuit (100) with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap (H1) of the decision feedback equalizer (112) is separated from the feedback of the remaining plurality of taps (H2, H3, ...). The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.

La présente invention concerne un dispositif d'échantillonnage ou de numérisation d'un signal de détection issu d'un détecteur de rayonnement X ou gamma dans lequel on réalise pendant une durée d'échantillonnage des estimations (140) d'un signal de rétroaction à des instants où ce signal qui est injecté en entrée inverseuse d'un comparateur est égal au signal de détection en entrée non-inverseuse, dudit comparateur.

Ce dispositif de quantification d'un signal analogique, appelé signal d'entrée, comporte un circuit électronique, appelé circuit d'analyse de signe (110), conçu pour fournir un premier bit du signal de sortie, appelé signal de signe (B_s), prenant une première valeur lorsque le signal d'entrée (V_e) est positif et une seconde valeur lorsque le signal d'entrée (V_e) est négatif.

Il comporte en outre un circuit électronique, appelé circuit d'analyse d'enveloppe (112), conçu pour fournir un second bit du signal de sortie, appelé bit de variation d'enveloppe (B_{var env}), prenant une première valeur, appelée valeur haute, lorsqu'un signal d'enveloppe (V_env) du signal d'entrée croît, et une seconde valeur, appelée valeur basse, lorsque le signal d'enveloppe (V_env) décroît.

Improved analog to digital and digital to analog signal processors are disclosed wherein a quick approximation of the input signal to the signal processor is attained and a more accurate approximation is later attained for the input signal. For the analog to digital conversion, a standard analog to digital converter having a finite resolution or a predetermined quantization error is used to create part of the digital representation. The remainder of digital representation is created by processing an error signal due to the finite resolution of a standard analog to digital converter and the infinite resolution of the analog input signal to a delta modulator. In a digital to analog signal processing circuit, the first part of the digital representation is converted by a standard digital to analog converter and the remaining portion is integrated into a frequency limited analog signal and then summed to reconstruct the analog signal. To avoid overshoot, the integrators of the signal processors are preset based upon the increase or the decrease in the first part. Further, the rate of integration is controlled so that the rate slows as the digital representation of the analog signal becomes increasingly more accurate representation of the input signal.