| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 121 | Bandpass-sampling delta-sigma demodulator | US13623350 | 2012-09-20 | US08717212B2 | 2014-05-06 | Phuong Huynh |
| An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As. | ||||||
| 122 | SPIN TORQUE TRANSFER MAGNETIC TUNNEL JUNCTION INTELLIGENT SENSING | US13420890 | 2012-03-15 | US20130245999A1 | 2013-09-19 | Abhishek Banerjee; Raghu Sagar Madala; Wenqing Wu; Kendrick H. Yuen; Chengzhi Pan |
| Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics. | ||||||
| 123 | Quantization device, radio-frequency receiver comprising such a device and quantization method | US13090527 | 2011-04-20 | US08471742B2 | 2013-06-25 | David Lachartre |
| A device for continuous time quantization of an input signal, in order to supply a continuous time output signal that is quantized as two bits, the device including: an electronic circuit, designed to supply a first bit of the output signal called the sign bit which at any time takes a first value when the input signal is positive and a second value when the input signal is negative, and an envelope analysis circuit designed to supply a second bit of the output signal called the envelope variation bit which at any time takes a first value, called high value, when an envelope signal of the input signal is increasing, and a second value, called low value, when the envelope signal is decreasing. | ||||||
| 124 | METHOD AND APPARATUS FOR PROVIDING RINGING TIMEOUT DISCONNECT SUPERVISION IN REMOTE TELEPHONE EXTENSIONS USING VOICE OVER PACKET-DATA-NETWORK SYSTEMS (VOPS) | US13405596 | 2012-02-27 | US20130058325A1 | 2013-03-07 | Wing-Kuen Chung; Cherng-Daw Hwang; Michael Tasker |
| A Multiservice Access Concentrator (MAC) provides a time limit for a first ringing voltage signal in response to an attempted call. The call is attempted via a voice over packet-data-network system (VOPS), wherein the VOPS comprises voice over Internet Protocol (IP), voice over Frame Relay, voice over Asynchronous Transfer Mode (ATM), and voice over High-level Data Link Control (HDLC) network systems. Generation of the first ringing voltage signal is terminated upon expiration of the time limit. A control message is transmitted to terminate the attempted call, wherein the control message is transmitted via the VOPS. | ||||||
| 125 | SIGMA-DELTA CONVERTER SYSTEM AND METHOD | US13305607 | 2011-11-28 | US20120194370A1 | 2012-08-02 | Giri NK Rangan; Roger Levinson; John M. Caruso |
| A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included. | ||||||
| 126 | Signal communication across an isolation barrier | US11674395 | 2007-02-13 | US07701731B2 | 2010-04-20 | Timothy A. Dhuyvetter; Sajol Ghoshal |
| A method for transmitting an information signal across an isolation barrier comprises receiving an input signal, preconditioning the input signal according to a modulation function, passing the preconditioned signal through the isolation barrier, and recovering the passed signal according to a demodulation function corresponding to the modulation function, the recovered signal being operative as a feedback signal. | ||||||
| 127 | Digital domain to pulse domain time encoder | US12118475 | 2008-05-09 | US07592939B1 | 2009-09-22 | Jose Cruz-Albrecht; Peter Petre |
| A system and method for making a digital encoder. The digital encoder has a digital-to-analog converter having multiple inputs and an output. The encoder also has an integrator having an input and an output, wherein the output of the digital-to-analog converter is connected to the input of the integrator. A quantizer has an input and an output, wherein the output of the integrator is connected to the input of the quantizer, and the output of the quantizer is connected to one of the plurality of inputs of the digital-to-analog converter. Methods to make the foregoing structure are also described. | ||||||
| 128 | Superconducting single flux quantum modulator circuit | US11808337 | 2007-06-08 | US07501877B2 | 2009-03-10 | Futoshi Furuta; Kazuo Saitoh |
| Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another. Moreover, by changing the density or phase of a SFQ pulse to be supplied to the Josephson junctions of the integration circuit, the correlativity of quantization noise between the outputs of the modulator circuits is eliminated so that the bit accuracy is improved. | ||||||
| 129 | Method and apparatus for encoding and decoding delta encoded information to locate live pointers in program data stacks | US847770 | 1997-04-23 | US5909579A | 1999-06-01 | Ole Agesen; David Ungar |
| Live pointer information for a stream of bytecodes is precomputed for each bytecode. The precomputed full live pointer information is stored only for bytecodes at predetermined intervals in the stream. Between the bytecodes for which full live pointer information is stored, changes in the live pointer information produced by each bytecode are encoded using a suitable compressive coding and stored. Later, when a program which needs the live pointer information, such as garbage collection, is initiated, the full live pointer information for the nearest bytecode preceding the desired bytecode boundary is retrieved along with the intervening coded changes. The changes are decoded and applied to the retrieved live pointer information to generate the live pointer information at the desired bytecode boundary. In one embodiment of the invention, the live pointer changes are delta encoded so that each code contains information relating to the live pointer changes produced by a bytecode from the live pointer information as modified by the previous delta code. In another embodiment of the invention, the delta coded changes are encoded with a Huffman encoding scheme. | ||||||
| 130 | Analog-to digital converter with delta-sigma modulator | US731963 | 1996-10-23 | US5907299A | 1999-05-25 | Robert S. Green; Keith L. Davis |
| An analog-to-digital converter according to the present invention comprising a comparator having first and second inputs, and an output, the comparator comparing an analog input voltage at the first input to a tracking voltage at the second input to place a digital output on the comparator output in response thereto, a voltage switching matrix having an input connected to the output of the comparator and an output, an integrator having an input connected to the output of the voltage switching matrix and an output connected to the second input of the comparator to complete a feedback loop and to provide the tracking signal to the second input of the comparator, and a digital filter coupled to the output of the comparator, the digital filter to form a digital output corresponding to the analog input signal at the first input of the comparator. | ||||||
| 131 | Method and apparatus for mixed analog and digital processing of delta modulated pulse streams including digital-to-analog conversion of a digital input signal | US997498 | 1992-12-28 | US5349353A | 1994-09-20 | Djuro G. Zrilic |
| A digital processing circuit and method includes a signal modulator connected to modulate a delta-modulated first input signal with a digital second input signal to produce a delta modulated output pulse stream. The digital output can be directly used for many purposes, or the digital output can be demodulated to produce an analog output signal using a low pass filter. Also, if desired, the delta modulated pulse first pulse stream can be generated from an analog signal input through use of a sigma-delta modulator. The signal modulator includes a plurality of switches, each operated by a respective bit of the digital second input signal to switch between the delta modulated first input signal and a known pulse sequence, such as an idle sequence, for delivery to a switch output. A plurality of adder circuits are connected in series to add the successive outputs of the plurality of switches to the delta modulated pulse first input signal to produce the delta modulated output pulse stream. Each of the adder circuits comprises a full binary adder and a D-type flip-flop, the full binary adder having two binary signal inputs and a carry input, and having a sum output and a carry output, the sum output being connected to the carry input through the D-type flip-flop. The known pulse sequence, such as the idle sequence is connected to the input of the first adder circuit. The circuit can be used for many purposes, for example, to provide a multiplying digital-to-analog signal converter, a precision attenuator, or the like, without a requirement for precision components, circuit matching or other special analog signal matching techniques. | ||||||
| 132 | Analog to digital and digital to analog signal processors | US528767 | 1990-05-24 | US5124706A | 1992-06-23 | Richard C. Gerdes |
| Improved analog to digital and digital to analog signal processors are disclosed wherein a quick approximation of the input signal to the signal processor is attained and a more accurate approximation is later attained for the input signal. For the analog to digital conversion, a standard analog to digital converter having a finite resolution or a predetermined quantization error is used to create part of the digital representation. The remainder of digital representation is created by processing an error signal due to the finite resolution of a standard analog to digital converter and the infinite resolution of the analog input signal to a delta modulator. In a digital to analog signal processing circuit, the first part of the digital representation is converted by a standard digital to analog converter and the remaining portion is integrated into a frequency limited analog signal and then summed to reconstruct the analog signal. To avoid overshoot, the integrators of the signal processors are preset based upon the increase or the decrease in the first part. Further, the rate of integration is controlled so that the rate slows as the digital representation of the analog signal becomes increasingly more accurate representation of the input signal. | ||||||
| 133 | Decoder for delta-modulated code | US580353 | 1990-09-07 | US5043729A | 1991-08-27 | Yoshiji Fujimoto |
| A decoder for decoding a delta-modulated code represented with binary digit "1" or "0" to convert it into an analog signal, wherein when the delta-modulated code takes the first value ("1" or "0"), a positive pulse signal is applied to an integrator to increase its accumulated value by a constant value and when the delta-modulated code takes the second value ("0" or "1"), a negative pulse signal is appied to the integrator to decrease its accumulated value by the constant value, and this accumulated value of the integrator is outputted as an analog signal which corresponds to a code train of the delta-modulated code. The decoder is characterized in that it has a pulse width modulater which limits an effective pulse width of the pulse signal by performing pulse width modulation of the positive or negative pulse signal in response to a control signal. | ||||||
| 134 | Analog to digital and digital to analog signal processors | US408086 | 1989-09-15 | US5021786A | 1991-06-04 | Richard C. Gerdes |
| Improved analog to digital and digital to analog signal processors are disclosed wherein a quick approximation of the input signal to the signal processor is attained and a more accurate approximation is later attained for the input signal. For the analog to digital conversion, a standard analog to digital converter having a finite resolution or a predetermined quantization error is used to create part of the digital representation. The remainder of digital representation is created by processing an error signal due to the finite resolution of a standard analog to digital converter and the infinite resolution of the analog input signal to a delta modulator. In a digital to analog signal processing circuit, the first part of the digital representation is converted by a standard digital to analog converter and the remaining portion is integrated into a frequency limited analog signal and then summed to reconstruct the analog signal. To avoid overshoot, the integrators of the signal processors are preset based upon the increase or the decrease in the first part. Further, the rate of integration is controlled so that the rate slows as the digital representation of the analog signal becomes increasingly more accurate representation of the input signal. | ||||||
| 135 | Modem with noise-reducing decoder in demodulation of encoded binary pulse signals representative of constant amplitude signals | US184318 | 1988-04-21 | US4958158A | 1990-09-18 | Motomu Hashizume; Yukoh Matsumoto |
| Modem comprising a delta modulation (DM) encoder and a DM decoder which has noise-reducing capability in the demodulation of encoded binary pulse signals representative of constant amplitude signals. The DM decoder includes a 1-click delay circuit operable in conjunction with a logic circuit and an integrator to produce a demodulated output signal which is the same as the preceding signal when the input signals to the DM encoder are constant amplitude signals, thereby eliminating are substantially reducing granular noise arising from a constant analog input to the modem without requiring a special filter. The logic circuit of the DM decoder may be an exclusive NOR gate which compares the 1-clock delayed binary pulse signal with the binary pulse signal and provides a control signal output based upon the comparison. The control signal output from the exclusive NOR gate controls the output of the integrator and enables the integrator to produce a substantially noise-free demodulated output signal. | ||||||
| 136 | Delta modulator with integrator having positive feedback | US218645 | 1988-07-13 | US4926178A | 1990-05-15 | A. Martin Mallinson |
| A delta modulator includes an integrator, a comparator for sensing the output of the integrator and a flip flop for synchronizing the comparator output to a clock signal and providing an error signal to the input of the integrator. The output of the delta modulator is a data stream having a time-averaged duty cycle that represents the input signal amplitude. The integrator includes an amplifier that is provided with positive feedback. Error caused by the finite open loop gain of the amplifier is cancelled by the positive feedback. As a result, high accuracy is achieved. The integrator amplifier is stabilized by the overall negative feedback of the delta modulator loop. | ||||||
| 137 | Delta modulator having optimized loop filter | US324232 | 1981-11-23 | US4467291A | 1984-08-21 | Engel Roza |
| A delta modulator comprising a feedback loop incorporating a cascade arrangement formed by a difference producer, a loop filter, a two-level quantizer, a clock pulse-controlled sampler and a feedback path. In order to optimize the signal/quantization noise ratio the minimum phase loop filter has such a phase characteristic that the phase shift in the feedback loop caused by the time delay of the sampler is replenished to approximately 180.degree. with a certain margin, in a frequency range up to a certain cut-off frequency, the phase of the loop filter being constant above the cut-off frequency. | ||||||
| 138 | High accuracy delta modulator | US216028 | 1980-12-12 | US4371850A | 1983-02-01 | Stefan H. Klement |
| A delta modulation circuit features a variable input voltage which is compared periodically with a quantized previous signal sample, resulting in a digitized output. The digitized output of the comparison controls the selective operation of a switching control circuit which, in turn, is clocked at a predetermined rate. The switching control circuit selectively applies a positive or a negative reference signal to the input of the quantizer from a common voltage reference source. A quantum charge is derived from the signal reference source then, through selective switching, that quantized charge is transferred in a positive or a negative direction to the input of a quantized charge memory device, resulting in the quantized last signal sample. | ||||||
| 139 | Delta modulation which partitions input signal into variable-time segments that are iteratively encoded | US965991 | 1978-12-04 | US4201958A | 1980-05-06 | Syed V. Ahamed |
| Conventional delta modulation techniques ignore information contained in the input signal which may be used advantageously in the encoding process. Improved delta modulation methods are disclosed which reduce bit rate and enhance error performance by partitioning the input signal into variable-length segments determined by preselected characteristics of the signal. Within each segment, iterative encoding is employed to develop the bit stream representing the encoded input signal. One particular partitioning method employs positive and negative signal peaks to establish segment boundaries and the encoding process is aided by the gradient of the signal within each segment. | ||||||
| 140 | Method and arrangement for controlling delta modulator idle-channel noise | US622084 | 1975-10-14 | US4025852A | 1977-05-24 | Yau-Chau Ching |
| The idle-channel noise of a delta modulator is controlled by controlling the relative step size imbalance, 0. The instantaneous magnitude of the delta modulator output signal is converted to a multibit word and a second multibit word, representing a predetermined number, N, is subtracted therefrom. The dc component of the difference word is converted to analog form, amplified and inverted, and fed back to the delta modulator input stage. As a result, .theta. .apprxeq. -N. The delta modulated signal may be converted to a pulse-code modulated (PCM) signal using a digital integrator having a leak, .beta., in which case .theta. .apprxeq. -.beta.N. At the same time, the dc component of the PCM signal is advantageously reduced substantially to zero. | ||||||
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