| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | Multifunction audio digitizer | US3795900D | 1971-11-09 | US3795900A | 1974-03-05 | MONFORD L |
| An illustrative embodiment of the present invention includes apparatus which simultaneously produces both direct delta modulation and pulse code modulation. An input signal, after amplification, is supplied to a window comparator which supplies a polarity control signal to gate the output of a clock to the appropriate input of a binary up-down counter depending on whether the slope of the input signal is positive or negative. The control signals provide direct delta modulation while the updown counter output provides pulse code modulation.
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| 142 | Charge parcelling integrator | US3754234D | 1971-10-18 | US3754234A | 1973-08-21 | LAANE R; MURPHY B |
| An integrator network for use in signal conversion systems uses charge parcelling techniques to transmit pulses to the integrating capacitor as quanta of charge. A compensation network corrects imbalances between the input pulses.
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| 143 | Delta-modulated transmission system with prediction of voice development and transmission of only coordination and error signals | US3569834D | 1967-06-14 | US3569834A | 1971-03-09 | DEBART HUBERT P |
| The invention concerns a method for reducing the bandwidth in a delta-modulated transmission system which consists in setting up a prediction table of future pulses, base upon the last pulses of the delta-modulated train of pulses, in setting up simultaneously at the transmission and at the reception ends, a second train of pulses of the same repetition rate as the first train, in feeding the receiver with an error signal each time the concordance between the predicted pulse and the corresponding delta pulse is not realized, in correcting consequently the train of pulses built at the receiving end for building up with accuracy the initial train of delta pulses and finally in deducing from it the signal, for example a vocal one.
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| 144 | Delta modulation encoders with randomized idle circuit noise | US3516022D | 1966-11-17 | US3516022A | 1970-06-02 | BROLIN STEPHEN J |
| 145 | Accelerometer system | US3508254D | 1967-04-26 | US3508254A | 1970-04-21 | ROSS LESTER M; GRIMME BROOKS H |
| 146 | Delta modulator using operational integration | US3461406D | 1966-07-05 | US3461406A | 1969-08-12 | KROLL BARNEY M |
| 147 | Delta modulator with uniform quantizing steps | US3453562D | 1966-06-14 | US3453562A | 1969-07-01 | MAGNUSKI HENRY |
| 148 | Delta modulation signal transmission system | US20056362 | 1962-06-06 | US3249870A | 1966-05-03 | ANTON GREEFKES JOHANNES |
| 149 | Differential code modulator | US29321663 | 1963-07-05 | US3225315A | 1965-12-21 | JOHANN HOLZER |
| 150 | Telecommunication system | US2215360 | 1960-04-14 | US3112369A | 1963-11-26 | WILLIAM SPARRENDAHL GUNNAR ERI |
| 151 | Binary pulse modulator | US63295057 | 1957-01-07 | US2859408A | 1958-11-04 | JOHANN HOLZER |
| 152 | Asymmetrical delta modulation system | US51372155 | 1955-06-07 | US2817061A | 1957-12-17 | BOWERS FRITZ K |
| 153 | Pulse-code modulator | US21648651 | 1951-03-20 | US2745063A | 1956-05-08 | DE JAGER FRANK |
| 154 | POWER-EFFICIENT FLASH QUANTIZER FOR DELTA SIGMA CONVERTER | US15914833 | 2018-03-07 | US20180309460A1 | 2018-10-25 | Abhishek Bandyopadhyay; Daniel Peter Canniff; Mariana Tosheva Markova; Edward Chapin Guthrie |
| A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times. | ||||||
| 155 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND PROGRAM | US15578406 | 2016-05-27 | US20180211675A1 | 2018-07-26 | Takao Fukui |
| The present technology relates to a signal processing apparatus, a signal processing method, and a program that permit switching between a plurality of DSD signals having different sampling frequencies using a simple configuration.An acquisition section acquires a digital audio signal having a given sampling frequency selected from among the plurality of digital audio signals acquired by delta-sigma modulating an audio signal at a plurality of sampling frequencies. An interpolation section subjects the acquired digital audio signal to a pre-interpolation process when the sampling frequency of the acquired digital audio signal is lower than an operating clock of a delta-sigma demodulator. The present technology is applicable, for example, to a signal processing apparatus. | ||||||
| 156 | Digital filter | US15316807 | 2015-05-15 | US09973171B2 | 2018-05-15 | Tetsuya Kajita |
| A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples. | ||||||
| 157 | COMPRESSIVE ENCODING APPARATUS, COMPRESSIVE ENCODING METHOD, DECODING APPARATUS, DECODING METHOD, AND PROGRAM | US15553362 | 2016-02-18 | US20180115322A1 | 2018-04-26 | Takao Fukui |
| The present disclosure relates to a compressive encoding apparatus, a compressive encoding method, a decoding apparatus, a decoding method, and a program which can provide a lossless compression technology having a higher compression rate. An encoding unit of the compressive encoding apparatus converts M bits of a ΔΣ-modulated digital signal into N bits (M>N) with reference to a first conversion table, and when the M bits are not able to be converted into the N bits with the first conversion table, converts the M bits into the N bits with reference to a second conversion table. When the number of bit patterns of the N bits is P, the first conversion table is a table storing (P−1) number of codes having higher generation frequencies for past bit patterns, and the second conversion table is a table storing (P−1) number of codes having higher generation frequencies for past bit patterns, which follow those of the first conversion table. The present disclosure is applicable to a compressive encoding apparatus that compressively encoding an audio signal, and the like, for example. | ||||||
| 158 | Delta modulator receive channel for capacitance measurement circuits | US15087625 | 2016-03-31 | US09923572B2 | 2018-03-20 | Rishi Raghav Bacchu; Kaveh Hosseini; Dermot MacSweeney; Paul M. Walsh; Kofi Makinwa |
| A circuit, system, and method for measuring capacitance are described. A current may be received at an input of a conversion circuit. The current may be converted to a voltage signal which may be used to create a negative feedback current to the input of the conversion circuit and which may be demodulated digitally to provide a static digital output representative of a capacitance. | ||||||
| 159 | Delta-sigma modulator and modulation method, transmission device, and transmission method | US15528164 | 2015-11-18 | US09887705B2 | 2018-02-06 | Masaaki Tanio; Shinichi Hori |
| The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal. | ||||||
| 160 | Method of manufacturing distortion compensation apparatus | US15307489 | 2015-02-26 | US09887704B2 | 2018-02-06 | Takashi Maehata |
| A distortion compensator 10 acquires an asymmetric component included in a 1-bit pulse train outputted from a DSM 6 on the basis of an analog signal as an output signal obtained from the 1-bit pulse train, and an IQ signal as an input signal to be inputted to the DSM 6, and performs distortion compensation on the basis of the asymmetric component. The distortion compensator 10 is caused to store therein asymmetric component data representing the acquired asymmetric component. When acquiring the asymmetric component, the distortion compensator 10 acquires, as an asymmetric component, a difference between an output baseband signal obtained by orthogonally demodulating the analog signal as the output signal, and an input baseband signal before being orthogonally modulated. | ||||||
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