| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Combined pacemaker delta modulator and bandpass filter | US891478 | 1986-08-01 | US4692719A | 1987-09-08 | Robert H. Whigham |
| A combined pacemaker delta modulator and bandpass filter which requires only one active device. The sense signal is applied through a conventional delta modulator capacitor to the minus input of a differential amplifier, and the conventional current sources are connected to the minus input. Instead of simply connecting the plus input to a reference potential, however, it is also coupled, through a resistor, to the input signal, and an RC network is connected across the two inputs. | ||||||
| 182 | Temperature and process variation compensation for a delta demodulation decoder | US734417 | 1985-05-15 | US4684898A | 1987-08-04 | Timothy A. Dhuyvetter |
| A circuit for processing the control signal inputs for a control data signal decoder wherein a reference voltage and a reference current are generated for use in processing a stream of control signal bits. The control signal data stream is filtered, buffered and exponentialed. The processing serves to cancel out variations in temperature, resistance, process variations and circuit voltages to yield a stable control signal current. | ||||||
| 183 | Analog-to-digital converter for seismic exploration using delta modulation | US443504 | 1982-11-22 | US4616349A | 1986-10-07 | Thomas E. Shirley |
| An analog-to-digital converter for use in seismic data processing applications is disclosed which features variants on delta modulation and delta-sigma modulation methods. A series of single bits is output by an analog-to-digital converter based on comparison of a predicted analog signal with the actual analog signal. A low pass filter and subsampling operation is applied to the output digital bits to provide digital words corresponding to the analog signal amplitude. Plural integrator stages are shown which allow reduction of quantization error. | ||||||
| 184 | Delta modulation decoder with charge quanta magnitude correction | US956550 | 1978-10-30 | US4224571A | 1980-09-23 | Eise C. Dijkmans |
| Delta modulation decoder comprising an integrating network provided with a first integrating capacitor which is on the one hand connected to an input terminal of the integrating network and on the other hand to ground potential through a second integrating capacitor. The 1-pulses and the 0-pulses of the delta modulation signal, applied to the decoder, are applied to a current source circuit generating a positive charging quantum in response to each 1-pulse and a negative charging quantum in response to each 0-pulse. Said charging quanta are applied to the input terminal of the integrating network through a correction network. This correction network is controlled by the voltage V.sub.C3 across the second integrating capacitor, so that, if V.sub.C3 is positive, the positive charging quanta are reduced and/or the negative charging quanta increased and that, if V.sub.C3 is negative, the positive charging quanta are increased and/or the negative charging quanta reduced. | ||||||
| 185 | Delta modulation detector | US830256 | 1977-09-02 | US4176321A | 1979-11-27 | Paul H. Horn |
| A detector for detecting a delta modulated signal includes a timing circuit, a counter and a decoder arranged to detect a delta modulated signal in electrically noisy environment. The timing circuit is used to provide a timing signal of a predetermined time interval over which the counter counts the transitions present in the delta modulated signal. The counter is used for counting the digital bit occurrences of the delta modulated signal within the predetermined time interval. The decoder responds to the timing signal and receives the count signals from the counter and provides a binary signal of first state when the count signal indicates the number of bit occurrences of the delta modulated signal is above a predetermined high level of count or below a predetermined number of low count and provides a binary signal of a second state when the count signal indicates that the number of the digital bit occurrences occur between the predetermined high level of count and the predetermined low level of count. The detector is further provided with a latch circuit which responds to the output of the decoder and a code detect signal representing detection of a predetermined code signal in delta modulated signal. The latch circuit is used to provide an output signal in response to the binary signal of the first state from the decoder and the code detect signal to signify proper reception of delta modulated signal. The above described detector may be advantageously used in a receiver for receiving a scrambled or unscrambled incoming delta modulated digital data signal. | ||||||
| 186 | High speed voice replay via digital delta modulation | US814591 | 1977-07-11 | US4091242A | 1978-05-23 | Francis Paul Carrubba; Walter Edgar Daniels, Jr.; Peter Anthony Franaszek |
| A method of and apparatus for time compression and changing the readout speed of a delta modulation encoded audio signal. The encoded audio signal has portions selectively deleted therefrom in accordance with detected zero crossovers of the same sign which occur in a predetermined timing sequence. The encoded audio signal which has had portions selectively deleted therefrom is decoded, with the undeleted decoded portions being joined. The undeleted portions have the same gain factor where joined, thereby eliminating step transients. | ||||||
| 187 | Method and circuit arrangement for adapting the measuring range of a measuring device operating with delta modulation in a navigation system | US654960 | 1976-02-03 | US4075701A | 1978-02-21 | Fritz Hofmann |
| A method and circuit arrangement for changing the sensitivity of the measng range in a device employing delta modulation in a navigation system. The device uses an integrator for integrating a measured value from a sensor, a threshold detector following the integrator, a synchronizer responsive to the threshold detector and a pulse transmitter driven by the synchronizer. The pulse transmitter provides a reset pulse with appropriate release time to reset the integrator, the reset pulse being counted by a counter fed to a navigation computer. A switching arrangement at the input of the integrator operates to change the sensitivity or scale factor. Switching is controlled by logic circuitry which responds to the level of the measured value as well as the output of the integrator. The reset pulse release time is also employed as a switching criterion. Means for providing a dynamic measured value and for taking into account the anticipated customary deflections of the sensor are included as additional switching criteria. Means for correcting for zero point error which includes means for changing input sensitivities are also disclosed. | ||||||
| 188 | Current control circuit with current proportional circuit | US666416 | 1976-03-12 | US4051428A | 1977-09-27 | Kunio Imai |
| A current control circuit comprises a current proportional circuit having two terminals, the current of one terminal being a proportional relationship with the current of the other terminal. An output terminal coupled with the current proportional circuit and a load through which a controlled current flows, and a constant current source. A steering circuit to which a switching signal is applied, is provided between the two terminals of the current proportional circuit and the constant current source, in order to couple the constant current source to one of the two terminals in response to the switching signal. | ||||||
| 189 | Delta modulation encoder | US552894 | 1975-02-25 | US4008435A | 1977-02-15 | Toshio Oshima; Tatsuo Ishiguro |
| A delta modulation encoder consisting essentially of a slope limiter and a delta modulator is disclosed. The slope limiter comprises an integrator, a subtraction circuit for generating the difference signal between the input analog signal and the output of the integrator, and an amplitude-limited amplifier, having preset saturation levels, for amplifying the output of the subtraction circuit and for supplying the amplified output to the integrator. The delta modulator encodes the output of the slope limiter into a delta-modulation signal. Thus, the slope of the input signal to the delta modulator is limited by the slope limiter to a value below the maximum slope which the delta modulator can follow. | ||||||
| 190 | Method and apparatus for suppressing background noise in a digital telephone system | US453635 | 1974-03-21 | US3995217A | 1976-11-30 | Peter Leslie Smith |
| An apparatus for suppressing background noise in a companded delta modulated telephone system. The apparatus includes a comparator for comparing a signal related to the analogue input signal to an encoder of the system with a reference signal. The comparator provides an output to reduce the rate of occurrence of a succession of bits which cause companding within the encoder when the reference signal exceeds the other signal to the comparator. This is achieved by altering the step size of a feedback signal within the encoder or modifying the output from the encoder by removing or inverting one of the compand bits. The reference signal is higher than a signal generated by background noise and consequently for signals below the reference signal the decoder reconstructs an analogue signal which is lower in level than the input signal. A method for achieving the result is also claimed. | ||||||
| 191 | Delta modulation system employing digital frame averaging | US559177 | 1975-03-17 | US3980953A | 1976-09-14 | W. Franklin Nance; Ronald J. Surprenant |
| A delta modulator produces a digital bit stream from an input analog waveform and applies same to bit-averaging circuitry dividing the bit stream into time-frame intervals and computing the average slope per frame. Each average time-frame slope value is transmitted over a communication system as a discrete digital signal and at a receiver each such signal is employed to set the gain of a multi-level integrator and thus incrementally reconstruct the original waveform. | ||||||
| 192 | Delta modulation circuitry with automatic squelch and gain control | US53090374 | 1974-12-09 | US3911363A | 1975-10-07 | PATTEN MICHAEL ALLEN |
| This delta modulating circuit arrangement is fully effective over a wide range of input signals through heavy background noise without periodic adjustment. The modulator circuit comprises an input comparator circuit driving a data-clocked flip-flop circuit that is flipped by a clocking pulse train. The output of the comparator circuit is integrated and applied to a differential amplifier circuit along with a positive or negative current obtained from the complementary output of the flip-flop circuit. The output of the differential amplifier is applied to the input of the comparator circuit. A balancing resistor is shunted across the differential amplifier circuit and adjusted to the mean between performance limits. An automatic gain controlled amplifying circuit is connected between the audio frequency input circuit and the comparator circuit to maintain the signal swing within the capabilities of the delta modulator circuit. Preferably, an optocoupler device is interposed between the amplifying and the comparator circuits for opening the circuit under control of a squelch control circuit to prevent modulating noise in the absence of signal.
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| 193 | Compound transistor connection loading for a current | US42102773 | 1973-12-03 | US3867650A | 1975-02-18 | BALDWIN GARY LEE |
| A differential amplifier type of current switch includes in series in the two current paths thereof the first and last stages, respectively, of a common collector type of compound transistor. Arrangements are shown for employing current switches of this type for controlling, a charge parceling bipolar, feedback integrator of a delta modulator.
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| 194 | Delta modulator having low-level random noise characteristic | US28392572 | 1972-08-25 | US3855555A | 1974-12-17 | BURKHARD M; PETERS R |
| A delta modulator for analog-digital conversion, comprising a high gain comparator amplifier connected to the input of a clockcontrolled sampling flip-flop circuit; an audio signal is applied to the input of the comparator and a principal integrating circuit of short time constant develops a replica of the audio signal from the output of the flip-flop, and applies the replica to the comparator in bucking relation to the original audio signal. A self-bias variable D.C. reference signal is derived from the flip-flop output and is applied to the other comparator input; the bias circuit also transmits a negative feedback A.C. signal of limited amplitude, asymmetrical with respect to polarity, introducing a limited amplitude broad-band random noise into the demodulated output signal for idling (zero or very small input) conditions.
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| 195 | Differential pulse code modulation apparatus | US19219871 | 1971-10-26 | US3825831A | 1974-07-23 | ISHIGURO T |
| A differential pulse code modulator includes a delta modulator for converting an analog input signal to a delta modulated signal, a digital filter for removing quantizing noise components, and a direct feedback pulse code modulation encoder. The feedback encoder includes a subtractor for determining the difference between a decoded digital signal and the output of the digital filter, a digital integrator for integrating the output of the subtractor, a digital coder for converting the output of the integrator to a differential pulse code modulation signal and a digital decoder for converting the differential signal to the decoded digital signal supplied to the subtractor. Clock pulses are supplied to the delta modulator, the digital filter, and the direct feedback pulse code modulation encoder.
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| 196 | Audio to digital converter | US3668559D | 1970-11-16 | US3668559A | 1972-06-06 | WILLIAMS RICHARD E; HOLFORD WARREN L |
| An audio-to-digital converter having a comparator means for comparing an audio input with a feedback signal. The feedback is coupled to the comparator through a feedback control device so that a constant comparison occurs.
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| 197 | Delta modulation encoder having double integration | US3624558D | 1970-01-16 | US3624558A | 1971-11-30 | BROLIN STEPHEN JOSEPH |
| A delta modulation encoder has a second integrator for producing more rapid alternations in the noise signal, thereby removing a portion of the noise from the signal frequency band. The integrator is clamped to prevent excessive overshoots.
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| 198 | High speed analog-to-digital converter | US26628363 | 1963-03-19 | US3273141A | 1966-09-13 | HACKETT KENNETH R |
| 199 | High speed delta encoder | US30975863 | 1963-09-18 | US3270335A | 1966-08-30 | HACKETT KENNETH R |
| 200 | Analog to incremental-digital converter | US29057463 | 1963-06-13 | US3246317A | 1966-04-12 | JOHNSON ROBERT S; WILLIAMSON JR FRANK R; HAMMOND JR JOSEPH L |
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