| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | DELTA-SIGMA MODULATOR AND MODULATION METHOD, TRANSMISSION DEVICE, AND TRANSMISSION METHOD | US15528164 | 2015-11-18 | US20170331491A1 | 2017-11-16 | Masaaki TANIO; Shinichi HORI |
| The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal. | ||||||
| 162 | DIGITAL FILTER | US15316807 | 2015-05-15 | US20170201236A1 | 2017-07-13 | Tetsuya KAJITA |
| A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples. | ||||||
| 163 | SIGNAL AMPLIFICATION AND TRANSMISSION BASED ON COMPLEX DELTA SIGMA MODULATOR | US15318067 | 2014-06-23 | US20170134055A1 | 2017-05-11 | Mojtaba Ebrahimi; Mohamed Helaoui; Fadhel Ghannouchi; Fahimi Elsayed; Bradley John Morris |
| Apparatuses and methods for power amplification and signal transmission using complex delta-sigma modulation are disclosed. In one embodiment, a complex delta sigma modulator unit comprising a complex polar quantizer within an integrator loop is disclosed. The complex polar quantizer quantizes the envelope of a complex integrated signal and produces a complex quantized output signal of substantially constant envelope. The complex quantized output signal is used in deriving a complex feedback signal within the integrator loop of the complex DSM. The complex quantized output signal may be used in driving a power amplifier substantially at saturation. In some embodiments, an adjacent channel power ratio (ACPR) enhancement technique is used to reduce the quantization noise in the complex quantized output signal. | ||||||
| 164 | SIGNAL PROCESSING APPARATUS AND METHOD | US15158001 | 2016-05-18 | US20170126216A1 | 2017-05-04 | JongPal KIM |
| A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal. | ||||||
| 165 | METHOD OF MANUFACTURING DISTORTION COMPENSATION APPARATUS | US15307489 | 2015-02-26 | US20170063391A1 | 2017-03-02 | Takashi MAEHATA |
| A distortion compensator 10 acquires an asymmetric component included in a 1-bit pulse train outputted from a DSM 6 on the basis of an analog signal as an output signal obtained from the 1-bit pulse train, and an IQ signal as an input signal to be inputted to the DSM 6, and performs distortion compensation on the basis of the asymmetric component. The distortion compensator 10 is caused to store therein asymmetric component data representing the acquired asymmetric component. When acquiring the asymmetric component, the distortion compensator 10 acquires, as an asymmetric component, a difference between an output baseband signal obtained by orthogonally demodulating the analog signal as the output signal, and an input baseband signal before being orthogonally modulated. | ||||||
| 166 | Superconductor analog to digital converter | US14522842 | 2014-10-24 | US09312878B1 | 2016-04-12 | Amol Inamdar; Deepnarayan Gupta |
| Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB. | ||||||
| 167 | Delta conversion analog to digital converter providing direct and quadrature output | US14319154 | 2014-06-30 | US09112522B2 | 2015-08-18 | Michael Harrison |
| Embodiments of the present invention are directed to an analog to digital converter, comprising a comparator for comparing an analog input signal and an analog feedback signal output from a digital to analog converter to generate a digital direct output signal, a summer, coupled to the comparator, for summing the digital output signal with a digital feedback signal to generate a summed signal, a first integrator, coupled to the summer, for integrating the summed signal to generate a direct output signal and a second integrator, coupled to the first integrator and to the summer, for integrating the direct output signal to generate the digital feedback signal as a quadrature output signal. | ||||||
| 168 | LEVEL DE-MULTEPLEXED DELTA SIGMA MODULATOR BASED TRANSMITTER | US13958088 | 2013-08-02 | US20150036766A1 | 2015-02-05 | Fahmi ELSAYED; Mohamed HELAOUI; Fadhel GHANNOUCHI; Mojtaba EBRAHIMI; Bradley John MORRIS |
| This specification discloses a level de-multiplexed DSM based transmitter and a method for providing the same. Broadly embodiments of the present specification enable wireless transmitters that are based on multi-level de-multiplexed DSM. A three-level de-multiplexed DSM based transmitter is disclosed as an example. More generally, the use of m-level de-multiplexed DSM is also taught, the specification thereby being enabling for broader applications to a person skilled in the art. At least one of the efficiency and linearity of transmitters can be enhanced as required for specific applications by a person of skill in the art in view of this specification and the teachings of its disclosed embodiments. | ||||||
| 169 | Time integrator and ΔΣ time-to-digital converter | US14447315 | 2014-07-30 | US08941526B2 | 2015-01-27 | Shiro Dosho; Masao Takayama; Takuji Miki |
| A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration. | ||||||
| 170 | DELTA CONVERSION ANALOG TO DIGITAL CONVERTER PROVIDING DIRECT AND QUADRATURE OUTPUT | US14319154 | 2014-06-30 | US20150009055A1 | 2015-01-08 | Michael Harrison |
| Embodiments of the present invention are directed to an analog to digital converter, comprising a comparator for comparing an analog input signal and an analog feedback signal output from a digital to analog converter to generate a digital direct output signal, a summer, coupled to the comparator, for summing the digital output signal with a digital feedback signal to generate a summed signal, a first integrator, coupled to the summer, for integrating the summed signal to generate a direct output signal and a second integrator, coupled to the first integrator and to the summer, for integrating the direct output signal to generate the digital feedback signal as a quadrature output signal. | ||||||
| 171 | Fast ADC for optical tape wobble signal | US14090249 | 2013-11-26 | US08923104B1 | 2014-12-30 | Faramarz Mahnad |
| An analog-to-digital converter includes a feedback loop that receives a wobble signal having a wobble signal frequency. The feedback loop includes a comparator that receives the wobble signal through a first resistive component at a first comparator input and outputs a first output signal having either a high output or a low output. The feedback loop also includes a sampling component that samples the first output signal at a sampling frequency and outputs a second output signal and a first integrator component that receives the second output signal and outputs a third output signal. The third output signal tracks the wobble signal due to feedback action in the feedback loop. Finally, the analog-to-digital converter further includes a final discrete integrator component that integrates the second output signal to provide a digital representation of the wobble signal. | ||||||
| 172 | Area-efficiency delta modulator for quantizing an analog signal | US13788518 | 2013-03-07 | US08842029B2 | 2014-09-23 | Chun-Yu Wu; Yuan-Fu Lyu |
| The invention comprises sample-and-hold circuit and digital-to-analog converter into a differentially operational unit. In analog-to-digital conversion unit, on the premise of fixed or non-fixed quantization error, analog-to-digital converter dynamically adjusts number of bits solved or size of quantized step according to the magnitude of differential voltage between sampled input signal and previously quantized input signal, thus this invention can reduce the non-necessary power consumption from redundant code and overload of input signal. Differentially operational unit and analog-to-digital unit share the same capacitor array which has binary-weighted arrangement to reduce circuit complexity and area. | ||||||
| 173 | A/D converter | US13558093 | 2012-07-25 | US08830097B2 | 2014-09-09 | Kenta Aruga; Takashi Miyazaki; Hiroyuki Tomura |
| An arithmetic operation circuit provided in a delta-sigma modulator of a delta-sigma A/D converter includes two reference capacitors which are respectively provided at a positive side input node and a negative side input node of an operational amplifier. When a signal corresponding to an output of the modulator is added or subtracted to or from an input signal, the amount of charge added to the input node of the operational amplifier is made to be always the same regardless of the reference voltage by complementarily switching the connection of the reference capacitors at the positive side input node and the negative side input node, and thereby the potential of the input node of the operational amplifier is made to converge to the common mode potential of the circuit. | ||||||
| 174 | ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND METHOD OF DRIVING THE SAME | US14116294 | 2013-02-21 | US20140077985A1 | 2014-03-20 | Yusuke Tokunaga |
| An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal. | ||||||
| 175 | BANDPASS-SAMPLING DELTA-SIGMA DEMODULATOR | US13623350 | 2012-09-20 | US20140077978A1 | 2014-03-20 | Phuong HUYNH |
| An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As. | ||||||
| 176 | Delta-Sigma D/A Converter | US13884639 | 2011-10-20 | US20130234872A1 | 2013-09-12 | Roberto Lugli; Michael Korn; Alfred Zotz; Stephan Damith |
| A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges. | ||||||
| 177 | ASYNCHRONOUS DIGITISATION OF TRANSIENT SIGNALS FROM RADIATION DETECTORS | US13713408 | 2012-12-13 | US20130147648A1 | 2013-06-13 | Guillaume MONTEMONT |
| A device for sampling or digitising a detection signal from an X- or gamma-ray detector wherein, during a sampling time, estimations of a feedback signal are made at times when the signal injected to the inverting input of a comparator is equal to the detection signal at the non-inverting input of said comparator. | ||||||
| 178 | Method and apparatus for providing ringing timeout disconnect supervision in remote telephone extensions using voice over packet-data-network systems (VOPS) | US12002922 | 2007-12-18 | US20080175233A1 | 2008-07-24 | Wing-Kuen Chung; Cherng-Daw Hwang; Michael Tasker |
| A Multiservice Access Concentrator (MAC) provides a time limit for a first ringing voltage signal in response to an attempted call. The call is attempted via a voice over packet-data-network system (VOPS), wherein the VOPS comprises voice over Internet Protocol (IP), voice over Frame Relay, voice over Asynchronous Transfer Mode (ATM), and voice over High-level Data Link Control (HDLC) network systems. Generation of the first ringing voltage signal is terminated upon expiration of the time limit. A control message is transmitted to terminate the attempted call, wherein the control message is transmitted via the VOPS. | ||||||
| 179 | Method and apparatus for providing ringing timeout disconnect supervision in remote telephone extensions using voice over packet-data-network systems (VOPS) | US09164429 | 1998-09-30 | US07339924B1 | 2008-03-04 | Wing-Kuen Chung; Cherng-Daw Hwang; Michael Tasker |
| A Multiservice Access Concentrator (MAC) provides a time limit for a first ringing voltage signal in response to an attempted call. The call is attempted via a voice over packet-data-network system (VOPS), wherein the VOPS comprises voice over Internet Protocol (IP), voice over Frame Relay, voice over Asynchronous Transfer Mode (ATM), and voice over High-level Data Link Control (HDLC) network systems. Generation of the first ringing voltage signal is terminated upon expiration of the time limit. A control message is transmitted to terminate the attempted call, wherein the control message is transmitted via the VOPS. | ||||||
| 180 | System for continuous-time modulation | US09478040 | 2000-01-05 | US06366229B2 | 2002-04-02 | Tom P. E. Broekaert |
| A continuous-time modulator comprises a modulator bridge having a bridge input terminal, an inverted bridge input terminal, a clock terminal and an inverted clock terminal. The modulator further comprises an input amplifier for amplifying an input signal and the input signal inverted and a bridge amplifier coupled to the input amplifier. The bridge is coupled to the bridge amplifier. The modulator further comprises a feedback amplifier coupled to the bridge, with the bridge amplifier coupled to the feedback amplifier. A clock amplifier for amplifying a clock signal and the clock signal inverted is also coupled to the bridge. An output signal is provided at an output terminal coupled to the bridge input terminal. An inverted output signal is provided at an output terminal coupled to the inverted bridge input terminal. | ||||||
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