| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 模拟数字转换电路及其驱动方法 | CN201380001301.X | 2013-02-21 | CN103518328A | 2014-01-15 | 徳永祐介 |
| 一种模拟数字转换电路以及其驱动方法。AD转换电路（10）具有生成时钟信号（211和212）的时钟生成电路（150）和使用时钟信号（211和212）进行动作的增量型的模拟数字转换器（100）。所述时钟信号（211和212）包括第1初始期间（T2）和多个通常期间（T3），该第1初始期间（T2）是高期间以及低期间中的一方的期间，并且是复位解除后的第1个期间，该通常期间（T3）位于该第1初始期间（T2）之后，并且是比该第1初始期间（T2）短的高期间或者低期间。 | ||||||
| 2 | 零差接收机的平衡压扩增量装置 | CN96193773.4 | 1996-03-01 | CN1183864A | 1998-06-03 | P·W·登特 |
| 揭示了一种平衡增量调制模数转换电路。第一主积分器产生第一输出信号,当产生第一控制信号时该信号上升,当产生第二控制信号时该信号下降。第二主积分器产生第二输出信号,当产生第一控制信号时该信号下降,当产生第二控制信号时该信号上升。然后基于第一和第二输出信号之间的差值产生第一和第二控制信号。 | ||||||
| 3 | 用于基于阈值的信号编码的异步脉冲调制 | CN201580033497.X | 2015-05-19 | CN106663220A | 2017-05-10 | Y·C·尹 |
| 一种信号处理方法包括：将输入信号与一个或多个正阈值以及一个或多个负阈值作比较。该方法还包括基于输入信号与(诸)正阈值和(诸)负阈值的比较来生成输出信号。该方法进一步包括将输出信号反馈至衰退重构滤波器以创建经重构信号并将经重构信号与输入信号组合。 | ||||||
| 4 | 具有判决反馈均衡的模拟时钟数据恢复电路中的相位检测 | CN201610440623.X | 2016-06-17 | CN106257437A | 2016-12-28 | 金文毅; J·雷恩; 李海昌 |
| 本发明的实施例涉及一种在具有判决反馈均衡的接收器电路中的相位检测的方法。部分均衡边沿信号和完全均衡边沿信号被生成。来自判决反馈均衡器的第一抽头的反馈与剩余的多个抽头的反馈分离。来自多个抽头(不包括第一抽头)的反馈被用于生成部分均衡边沿信号，而来自所有抽头的反馈被用于生成完全均衡边沿信号。部分均衡边沿信号和完全均衡边沿信号被相位检测电路用来提供用于改进的性能的高度准确的数据采样位置。 | ||||||
| 5 | A/D转换器 | CN201210275497.9 | 2012-07-31 | CN102983865B | 2016-01-20 | 有贺健太; 宫崎敬史; 户村宏行 |
| 本发明涉及A/D转换器。在Δ-ΣA/D转换器的Δ-Σ调制器中提供的算术运算电路包括分别设置在运算放大器的正侧输入节点和负侧输入节点处的两个基准电容器。当与调制器的输出相对应的信号与输入信号相加或相减时，通过互补地切换正侧输入节点和负侧输入节点处的基准电容器的连接，使得增加到运算放大器的输入节点的电荷量总是相同，而无论基准电压如何，从而使运算放大器的输入节点的电位收敛到该电路的共模电位。 | ||||||
| 6 | 一种全差分放大器输出共模失调校正电路 | CN201410767406.2 | 2014-12-12 | CN104410377A | 2015-03-11 | 蒋仁杰 |
| 本发明公开了一种带输出共模失调校正的增益可编程的全差分放大器。本电路由两个单端放大器AMP1、AMP2以及一个电阻R0组成，通过改变运放内的电阻R2、R3、R5、R6可以改变输出共模电平，从而实现一种全差分放大器输出共模失调校正。 | ||||||
| 7 | 德耳塔西格玛D/A转换器 | CN201180054620.8 | 2011-10-20 | CN103222196B | 2016-10-19 | 罗伯特·卢格力; 迈克尔·科恩; 阿尔弗雷德·佐兹; 斯特凡·达米特 |
| 本发明涉及德耳塔西格玛D/A转换器（48），利用该德耳塔西格玛D/A转换器，可以把数字化值的输入信号转换为与一个周期相对应的时间离散的双态输出信号。在该处理中，可以使用已经在几个周期上形成的输出信号的平均值来产生输入信号值的模拟表示。该德耳塔西格玛D/A转换器（48）被实施以使得在使用期间，所述转换器通过信号图案集合的信号图案串接在一起而提供输出信号，其中，该集合的信号图案每一个是与周期相对应的双态时间离散的，并且在几个周期的信号图案周期长度上延伸。该集合的至少两个信号图案具有彼此不同的信号图案平均值，并且形成在相应的信号图案周期长度上，并且该集合的所有信号图案的每一个具有大致相同数目的、特别是精确相同数目的沿。 | ||||||
| 8 | 德耳塔西格玛D/A转换器 | CN201180054620.8 | 2011-10-20 | CN103222196A | 2013-07-24 | 罗伯特·卢格力; 迈克尔·科恩; 阿尔弗雷德·佐兹; 斯特凡·达米特 |
| 本发明涉及德耳塔西格玛D/A转换器（48），利用该德耳塔西格玛D/A转换器，可以把数字化值的输入信号转换为与一个周期相对应的时间离散的双态输出信号。在该处理中，可以使用已经在几个周期上形成的输出信号的平均值来产生输入信号值的模拟表示。该德耳塔西格玛D/A转换器（48）被实施以使得在使用期间，所述转换器通过信号图案集合的信号图案串接在一起而提供输出信号，其中，该集合的信号图案每一个是与周期相对应的双态时间离散的，并且在几个周期的信号图案周期长度上延伸。该集合的至少两个信号图案具有彼此不同的信号图案平均值，并且形成在相应的信号图案周期长度上，并且该集合的所有信号图案的每一个具有大致相同数目的、特别是精确相同数目的沿。 | ||||||
| 9 | A/D转换器 | CN201210275497.9 | 2012-07-31 | CN102983865A | 2013-03-20 | 有贺健太; 宫崎敬史; 户村宏行 |
| 本发明涉及A/D转换器。在Δ-ΣA/D转换器的Δ-Σ调制器中提供的算术运算电路包括分别设置在运算放大器的正侧输入节点和负侧输入节点处的两个基准电容器。当与调制器的输出相对应的信号与输入信号相加或相减时，通过互补地切换正侧输入节点和负侧输入节点处的基准电容器的连接，使得增加到运算放大器的输入节点的电荷量总是相同，而无论基准电压如何，从而使运算放大器的输入节点的电位收敛到该电路的共模电位。 | ||||||
| 10 | 델타 시그마 아날로그 디지털 컨버터 | KR1020080040484 | 2008-04-30 | KR1020090114706A | 2009-11-04 | 김성우; 김영식 |
| PURPOSE: A delta-sigma analog digital converter is provided to minimize a noise level in a passband by controlling a zero point of a signal transfer function and noise transfer function independently. CONSTITUTION: In a delta-sigma analog digital converter, an adder(110) unites an input signal and a feedback signal. A forward loop filter(120) converts an output signal of the adder. The forward loop filter filters the signal outputted from the adder. A quantizer(130) quantizes the signal outputted from the forward loop filter, and the feedback loop filter(140) converts the signal outputted from the quantizer. The feedback loop filter outputs a changed signal. A controller controls the forward loop filter and determines a zero point of a transfer function of the forward loop filter according to interference signal information. | ||||||
| 11 | LEVEL DE-MULTIPLEXED DELTA SIGMA MODULATOR BASED TRANSMITTER | EP14767134.1 | 2014-08-04 | EP3028387B1 | 2018-02-28 | MOJTABA, Ebrahimi; MORRIS, Bradley John; ELSAYED, Fahmi; HELAOUI, Mohamed; GHANNOUCHI, Fadhel |
| This specification discloses a level de-multiplexed DSM based transmitter and a method for providing the same. Broadly embodiments of the present specification enable wireless transmitters that are based on multi-level de-multiplexed DSM. A three-level de-multiplexed DSM based transmitter is disclosed as an example. More generally, the use of m-level de-multiplexed DSM is also taught, the specification thereby being enabling for broader applications to a person skilled in the art. At least one of the efficiency and linearity of transmitters can be enhanced as required for specific applications by a person of skill in the art in view of this specification and the teachings of its disclosed embodiments. | ||||||
| 12 | Anordnung zur Kompensation einer Offset-Spannung und Verfahren | EP14199336.0 | 2014-12-19 | EP3035528A1 | 2016-06-22 | Prochaska, Dirk |
Die Erfindung betrifft eine Anordnung (1) zur Kompensation einer Offset-Spannung (Uoff) eines elektronischen Verstärkers (2), umfassend |
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| 13 | LEVEL DE-MULTIPLEXED DELTA SIGMA MODULATOR BASED TRANSMITTER | EP14767134.1 | 2014-08-04 | EP3028387A2 | 2016-06-08 | MOJTABA, Ebrahimi; MORRIS, Bradley John; ELSAYED, Fahmi; HELAOUI, Mohamed; GHANNOUCHI, Fadhel |
| This specification discloses a level de-multiplexed DSM based transmitter and a method for providing the same. Broadly embodiments of the present specification enable wireless transmitters that are based on multi-level de-multiplexed DSM. A three-level de-multiplexed DSM based transmitter is disclosed as an example. More generally, the use of m-level de-multiplexed DSM is also taught, the specification thereby being enabling for broader applications to a person skilled in the art. At least one of the efficiency and linearity of transmitters can be enhanced as required for specific applications by a person of skill in the art in view of this specification and the teachings of its disclosed embodiments. | ||||||
| 14 | DELTA-SIGMA-D/A-WANDLER | EP11771173.9 | 2011-10-20 | EP2638634A2 | 2013-09-18 | LUGLI, Robert; KORN, Michael; ZOTZ, Alfred; DAMITH, Stephan |
| The invention relates to a delta sigma D/A converter (48) by means of which a digitally valued input signal can be converted to a binary output signal that is time-discrete corresponding to one cycle. In the process, an analog representation of the value of the input signal can be produced using a mean value of the output signal, which has been formed over several cycles. The delta sigma D/A converter (48) is designed such that, during use, said converter provides the output signal by stringing together signal patterns of a set of signal patterns, wherein the signal patterns of the set are each binary, time-discrete corresponding to the cycle, and extend over a signal pattern cycle length of several cycles. At least two signal patterns of the set have signal pattern mean values which are different from each other, and which are formed over the respective signal pattern cycle length, and all the signal patterns of the set each have substantially the same number, in particular precisely the same number, of flanks. | ||||||
| 15 | Delta-sigma analog-to-digital converter and method for operating the same. | EP10305788.1 | 2010-07-16 | EP2408113B1 | 2013-03-06 | Goulier, Julien; Andre, Eric |
| 16 | Improved analog to digital and digital to analog signal processors | EP91304417.8 | 1991-05-16 | EP0458527A3 | 1993-03-31 | Gerdes, Richard Conwell |
Improved analog to digital and digital to analog signal processors are disclosed wherein a quick approximation of the input signal to the signal processor is attained and a more accurate approximation is later attained for the input signal. For the analog to digital conversion, a standard analog to digital converter having a finite resolution or a predetermined quantization error is used to create part of the digital representation. The remainder of digital representation is created by processing an error signal due to the finite resolution of a standard analog to digital converter and the infinite resolution of the analog input signal to a delta modulator. In a digital to analog signal processing circuit, the first part of the digital representation is converted by a standard digital to analog converter and the remaining portion is integrated into a frequency limited analog signal and then summed to reconstruct the analog signal. To avoid overshoot, the integrators of the signal processors are preset based upon the increase or the decrease in the first part. Further, the rate of integration is controlled so that the rate slows as the digital representation of the analog signal becomes increasingly more accurate representation of the input signal. |
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| 17 | ENHANCED DELTA MODULATION ENCODER | EP82902232.6 | 1982-06-04 | EP0081568B1 | 1986-10-29 | HARRIS, Robert W. |
| An enhanced delta modulation encoder (10) includes a spectrum tilter (24), a 1 bit analog-to-digital converter (26), a sampling circuit (28) and an internal decoder (22). An analog input signal and an internal analog signal from the internal decoder (22) are summed to provide an analog dither signal. The analog dither signal is tilted by the spectrum tilter (24) and is provided to the 1 bit analog-to-digital converter (26) which generates a digital signal. The sampling circuit (22) receives the digital signal from the analog-to-digital converter (26) and generates a digital output which is fed back to the internal decoder (22). The spectrum tilter (24) comprises at least three integrator circuits (38, 56, 58) and a clipping circuit (36). The three integrator circuits (38, 56, 58) tilt the frequency spectrum of noise above the maximum frequency of interest, the clipping circuit (36) prevents the encoder from becoming unstable. | ||||||
| 18 | PHASE DETECTION IN AN ANALOG CLOCK DATA RECOVERY CIRCUIT WITH DECISION FEEDBACK EQUALIZATION | EP16174580.7 | 2016-06-15 | EP3107239B1 | 2018-05-09 | JIN, Wenyi; REN, Jihong; LEE, Hae-Chang |
| An embodiment of the invention relates to a method of phase detection in a receiver circuit (100) with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap (H1) of the decision feedback equalizer (112) is separated from the feedback of the remaining plurality of taps (H2, H3, ...). The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance. | ||||||
| 19 | SIGNAL PROCESSING APPARATUS AND METHOD | EP16183655.6 | 2016-08-11 | EP3165159A3 | 2017-09-13 | KIM, Jong Pal |
A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplifed difference signal to a digital signal and summing the digital signal.
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| 20 | BAND-PASS FILTER | EP16151107.6 | 2016-01-13 | EP3193448A1 | 2017-07-19 | Liu, Shih-Chii; Yang, Minhao |
A band-pass filter (13) is described comprising a first first-order filter stage comprising a first resistor (R1) characterised by a first impedance and connected to a first node (25), referred to as a filter input node, and, through a second node (27) to a first reactive component (C1) connected to a third node (29), the first impedance being such that a first current therethrough is dependent on the difference between the voltages at the first and second nodes (25, 27); and a second first-order filter stage comprising a second resistor (R2*) characterised by a second impedance and connected to the second node (27), and, through a fourth node (31), to a second reactive component (C2) connected to a fifth node (33). The second impedance (R2) is such that a second current therethrough is dependent on the negative of the sum of the voltages at the second and fourth nodes (27, 31). The band-pass filter (13) further comprises summing means (23) for summing the voltages at the second and fourth nodes (27, 31) to output a voltage at a sixth node (35).
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