| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 81 | Time-to-digital converter with built-in self test | US12684771 | 2010-01-08 | US08072361B2 | 2011-12-06 | Stephan Henzler |
| Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices. | ||||||
| 82 | Zero point correction circuit of load meter | US11367769 | 2006-03-03 | US20060288882A1 | 2006-12-28 | Hiroyuki Moriya |
| The present invention relates to a zero point correction circuit for a load meter used for a press machine or the like, and more particularly to a configuration with which a zero point correction is made a plurality of times after a predetermined amount of time elapses, after press processing is performed, and a zero point correction value is set by calculating an average value of measured values. The predetermined amount of time is measured, for example, with an internal timer or the like, a sampling process is performed after the predetermined amount of time elapses, and an average value of sampled values is calculated and set as a zero point correction value, whereby an accurate zero point correction value can be obtained. | ||||||
| 83 | Method of determining measuring time for an analog-digital converter | US09891788 | 2001-06-26 | US20020030616A1 | 2002-03-14 | Tomonobu Hiramatsu; Shinichi Tanida |
| In order to shorten the measuring time of an analog-digital converter for measuring very small currents with its resolution unchanged, a method of determining the measuring time for the analog-digital converter which comprises the steps of preliminarily measuring current to be measured, determining a voltage range and a current range used for measurement, and determining the measuring time for an analog-digital converter for current measurement on the basis of the determined voltage and current ranges, and the measured current value is provided. | ||||||
| 84 | Digital-to-analog converter using a feedback element matching technique | US361437 | 1982-03-24 | US4549166A | 1985-10-22 | Masao Hotta; Kenji Maio; Hiromi Nagaishi |
| The present invention is characterized that a digital-to-analog converter having ordinal accuracy and one or more current sources are combined and the output currents of the current sources are accurately controlled to have a predetermined relationship with regard to the reference current which is a full-scale value of the analog output current of DAC so that the output current of the current sources designated by bits added to the superior bit of the digital input signal depending on the number of the current sources and the analog output current in response to the digital input signal with the added bits are added to produce an analog signal corresponding to the digital input signal. | ||||||
| 85 | A-D Converter and method of A-D conversion | US419571 | 1982-09-17 | US4521763A | 1985-06-04 | Yutaka Murao; Taira Nishizono |
| An A-D converter for converting into a pulse train signal an analog input voltage signal from a signal source, said A-D converter comprising a signal generator for providing a low analog input voltage signal of a low fixed level V.sub.L, a signal generator for providing a high analog input voltage signal of a high fixed level V.sub.H, a multiplexer connected to the signal source and the signal generators for receiving the signals therefrom and supplying the signals selectively and successively, a V-T converter connected to the multiplexer for converting a selected one of the analog input voltage signals into a pulse train signal; a memory for storing instruction programs used for A-D conversion, a central processing unit, a first counter connected to the V-T converter for counting pulses of the pulse train signal, said first counter being loaded with a specific value supplied from the central processing unit, a clock pulse generator for producing clock pulse, a second counter connected to the clock pulse generator for counting the clock pulses while the first counter is counting the same and a control circuit. | ||||||
| 86 | Analog-to-digital converter apparatus for condition responsive transducer | US155362 | 1980-06-02 | US4484177A | 1984-11-20 | Francis M. Jobbagy |
| An analog signal representing the measured output of a condition responsive transducer is supplied to a dual slope integrating analog-to-digital converter also receiving a regulated constant reference signal. Using the integrator in a non-inverting mode, the A/D converter operates in a single conversion cycle by first positively integrating a value of analog signal below a maximum negative input voltage for a fixed time period and then negatively integrating a voltage signal corresponding to the differential between the reference voltage signal and the maximum voltage for a variable time period to a comparative threshold. During integration, digital counts proportional to the variable integration period are accumulated and emitted for operating a digital device such as a digital display.Digital linearization of the converter output can optionally be provided by use of a programmed microcomputer reading a programmable-read-only-memory (PROM) to run a variable frequency clock. The clock is regulated to effect a frist phase converter time corresponding with an even multiple of the power line frequency. | ||||||
| 87 | Borehole spectral analog to digital converter | US312053 | 1981-10-16 | US4481597A | 1984-11-06 | Carl A. Robbins |
| For use with a photomultiplier tube responding to gamma ray induced scintillation pulses in a well logging sonde, a system having the preferred and illustrated embodiment of an input amplifier DC connected with a differential amplifier output to an integrating amplifier. The integrating amplifier is output to another differential amplifier then output to a sample and hold amplifier. This provides the input for a successive approximation digitizer. A feedback loop is incorporated in the system connected from the output of the integrating amplifier. It detects an error component due to noise, offset voltage, and drift accumulated at the integrator. It comprises a track and hold amplifier which is output to a pair of voltage comparators, one determining an excessive negative value and the other determining an excessive positive value. The two comparators are input to appropriate up and down terminals of a bidirectional counter. The counter is output to a digital to analog converter which forms a feedback analog voltage for the differential amplifier. The scintillation pulses are integrated over a specified time interval. That value is digitized after selection by the sample and hold amplifier. Moreover, base line drift is eliminated by operation of the feedback loop. | ||||||
| 88 | Method and device for the automatic calibration of an analog-to-digital converter | US183523 | 1980-09-02 | US4371868A | 1983-02-01 | Robert E. J. Van de Grift; Rudy J. Van de Plassche; Eise C. Dijkmans |
| For the automatic calibration of an analog-to-digital converter an analog calibration quantity is measured and the digital signal is compared with a digital calibration signal associated with the calibration quantity. A digital difference signal is applied to a register for influencing its counting capacity, while the register contents of pulses counted during the measurement also represents one of the parameters involved in the analog-to-digital conversion. Because of the fully digital character of the calibration, this calibration can be performed very rapidly and accurately. | ||||||
| 89 | Self-zeroing analog-to-digital conversion system | US498500 | 1974-08-19 | US3982241A | 1976-09-21 | Jesse B. Lipcon |
| A self-zeroing, drift-free analog-to-digital conversion system is disclosed in which a single amplifier is shared between an analog-to-digital converter circuit and a sample-and-hold circuit. The offset errors generated by the sample-and-hold circuit cancel with the offset errors generated by the analog-to-digital converter circuit since the circuitry introducing the offset errors is shared. As a result, system offset errors are negated and the system enables changing from a unipolar to bipolar input range without inclusion of any additional circuitry. Usage of a gain preamplifier is provided with no corresponding system offset errors being introduced. moreover, usage of a differential-input gain preamplifier is also provided, with the self-zeroing feature resulting in greatly improved common-mode rejection. | ||||||
| 90 | Offset control in autozeroing circuits for analog-to-digital converters | US534149 | 1974-12-18 | US3958236A | 1976-05-18 | Austin T. Kelly |
| A dual slope analog-to-digital converter, which has an autozeroing circuit for cancelling out integrator and detector offset and drift, is additionally provided with a circuit for injecting a voltage of selected polarity and magnitude to offset the input voltage of the converter such that the input voltage can be measured with respect to a nonzero reference line. | ||||||
| 91 | An error correcting encoder | US3775747D | 1972-10-17 | US3775747A | 1973-11-27 | GABRIEL M; ANDERSON D |
| This relates to an error correcting PCM encoder. The encoder is of the feedback comparison type. Logic circuitry is employed to make error corrections toward the end of the encoding cycle. The encoder receives an analog input signal carrying information to be coded. The encoder produces an initial code signal representative of the information to be coded. An analog replica of the initial code signal is compared with the analog input signal. An error signal is produced if the analog input signal and the analog replica of the initial code signal differ. The initial code signal is corrected in response to the error signal to produce an error corrected output code signal.
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| 92 | Self-calibrating analog to digital converter with predetermined transfer characteristics | US3685048D | 1970-09-30 | US3685048A | 1972-08-15 | PINCUS RALPH M |
| An analog to digital converter having self-calibrating capability throughout its range at every desired point and including means for providing an analog to digital transfer function with variable offset and slope.
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| 93 | Matrix for the coordinate detection of point source radiation in a two-dimensional plane | US3539995D | 1968-02-12 | US3539995A | 1970-11-10 | BRANDT RAYMOND A |
| 94 | 영점 보정 시스템 및 이를 이용한 영점 보정 방법 | KR1020160134198 | 2016-10-17 | KR101711875B1 | 2017-03-03 | 김경환 |
| 본발명은영점보정시스템에관한것으로써, 아날로그신호를디지털신호로변환시키는 AD(Analog To Digital)변환장치에내장되는영점보정시스템에있어서, 영점신호를생성하는영점신호생성부; 아날로그신호를생성하는아날로그신호생성부; 상기영점신호와상기아날로그신호를입력받는스위치부; 상기스위치부로부터전달받은상기영점신호를변환하여제1디지털신호를생성하거나, 상기스위치부로부터전달받은상기아날로그신호를변환하여제2디지털신호를생성하는변환부; 및상기제1디지털신호를기초로상기제2디지털신호를보정하여제3디지털신호를생성하는제어부를포함하되, 상기제어부는, 상기영점신호가상기변환부로입력되거나, 상기아날로그신호가상기변환부로입력되도록상기스위치부를제어하며, 상기제3디지털신호는, 상기제2디지털신호의값에서상기제1디지털신호의값을차감한값인것을특징으로한다.본발명에따르면, AD변환시에발생되는신호의편차가효과적으로보정될수 있다. 이에따르면, 영점편차를위한별도의튜닝과정이실시될필요가없기때문에, 기기생산과정의효율성이크게향상될뿐만아니라, 외부환경및 내부회로소자의노후화등의영향에도안정적인기기의동작이보장되므로, 기기의신뢰성이크게향상되는효과가있다.또한, 본발명에따르면, 생산라인에복수개의기기를설치하는경우, 동일한디지털출력이담보되어생산라인의생산성이크게향상될수 있는효과가있다. | ||||||
| 95 | 2－와이어 인터페이스를 구비한 아날로그 프론트 엔드 디바이스 | KR1020147015814 | 2012-11-09 | KR1020140101772A | 2014-08-20 | 퀴쿠엠포익스,빈센트 |
| 아날로그 프론트 엔드(AFE) 디바이스는, 적어도 하나의 프로그램가능 아날로그-디지털 변환기(ADC) 및 양방향 직렬 인터페이스 모드 및 단방향 2 와이어 인터페이스 모드로 동작하도록 스위치가능한 직렬 인터페이스를 갖고, 여기서 상기 단방향 2 와이어 직렬 인터페이스 모드는 단지 클럭 입력 및 데이터 출력 신호 라인을 사용하고, 상기 ADC는 상기 클럭 입력에 공급된 클럭에 동기하여 상기 단방향 2 와이어 직렬 인터페이스 모드에서 동작한다.
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| 96 | 반도체 장치의 오프셋 보정 회로 | KR1019990000186 | 1999-01-07 | KR1020000050366A | 2000-08-05 | 최진섭 |
| PURPOSE: An offset compensating circuit of a semiconductor device is provided to prevent noise and current consumption by reducing a DC offset voltage generated to the output terminals of a filter within an offset allowable range. CONSTITUTION: A filter(100) inputs a first input signal and a second input signal complementary to the first input signal, filters the first and second input signals to be outputted as first and second output signals. A programmable amplifier(200) amplifies the first and second output signals to output first and second amplified output signals in response to a comparison signal. An offset compensating circuit(300) supplies the comparison signal to the programmable amplifier(200) and is disabled when the filter and the programmable amplifier(200) are normally operated. | ||||||
| 97 | 데이터 획득 시스템 | KR1019810000251 | 1981-01-28 | KR1019850000486B1 | 1985-04-08 | 교지아이.벤크서 |
| The system uses a numbmer of parallel channels of communication, each including a voltage-to-frequency converter, and a central clock synchronously timed for each channel. The derivation of the train of pulses having a number of pulses representative of the magnitude of an analoge signal is fed into the V/F converter. The central clock also times the multiplexing at the measuring point of either the analog input signal or a bias voltage for calibration or a voltage reference for scaling. | ||||||
| 98 | 데이터 획득 시스템 | KR1019810000251 | 1981-01-28 | KR1019830005599A | 1983-08-20 | 교지아이.벤크서 |
| 내용없음 | ||||||
| 99 | APPARATUS FOR APPLYING DIFFERENT TRANSFER FUNCTIONS TO CODE SEGMENTS OF MULTI-BIT OUTPUT CODE THAT ARE SEQUENTIALLY DETERMINED AND OUTPUT BY MULTI-BIT QUANTIZER AND ASSOCIATED DELTA-SIGMA MODULATOR | US16190168 | 2018-11-14 | US20190199368A1 | 2019-06-27 | Chan-Hsiang Weng; Tien-Yu Lo |
| A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment. | ||||||
| 100 | Method and apparatus for preventing inherent error propagation of successive approximation register analog-to-digital converter through digital correction | US16001991 | 2018-06-07 | US20190044529A1 | 2019-02-07 | Mario Traeber |
| A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result. | ||||||
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