| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | 모터의 전류 제어 장치 및 그 방법 | KR1020140175351 | 2014-12-08 | KR1020160069416A | 2016-06-16 | 한선미; 김현균 |
| 본발명은모터의전류제어장치및 그방법에관한것으로, 모터구동신호에따라모터에전력을공급하는모터제어부, 상기모터로부터출력되는모터전류를감지하는전류감지부, 상기모터전류를기 설정된대역으로필터링하는저역필터(Low Pass Filter), 상기필터링된모터전류를근거로상기모터에인가된실측전류값을산출하고, 기설정된목표전류값과상기실측전류값의차이값에따라가변(dynamic)영역과정적(static)영역으로구분하며, 상기구분된영역에따라 ADC(Analog-Digital Converter)의샘플링(sampling)을위한인터럽트시간을설정하고, 상기설정된인터럽트시간에따라 ADC의샘플링횟수를조절하는마이컴을포함한다. | ||||||
| 42 | ＤＣ 오프셋 보상 방법 및 ＤＣ 오프셋 보상 장치 | KR1020077014411 | 2005-01-04 | KR1020070086622A | 2007-08-27 | 이시까와,히로요시; 후다바,노부까즈; 나가따니,가즈오; 하마다,하지메; 구보,도꾸로 |
| There is provided a method for accurately compensating a DC offset component contained in a signal to be modulated, i.e. a transmission signal generated in a quadrature modulation system. A DC offset correction value determined from the transmission signal is subjected to weighting in accordance with the signal level of an input signal to the quadrature modulation system as transmission data, and then the DC offset component contained in the transmission signal is compensated based on the weighted DC offset correction value. | ||||||
| 43 | 하중계의 영점보정회로 | KR1020060021632 | 2006-03-08 | KR1020060097629A | 2006-09-14 | 모리야히로유키 |
| 본 발명은 프레스기계 등에 사용되는 하중계의 영점보정회로에 관한 것이고, 특히 프레스가공종료 후, 일정시간을 경과한 후, 복수회의 영점보정의 측정을 실행하며, 해당 측정값의 평균값을 계산하여 영점보정값으로 하는 구성이고, 예를 들면 내부타이머 등으로 일정시간을 계수하며, 일정시간 경과 후, 샘플링처리를 실행하고, 해당 샘플링 값의 평균값을 산출하며, 해당 평균값을 영점보정값으로 하므로, 정확한 영점보정값을 얻을 수 있다. 하중계, 영점보정, 센서, 증폭기, 아날로그/디지털변환기, 조정기 | ||||||
| 44 | CALIBRATING TIMING, GAIN AND BANDWITH MISMATCH IN INTERLEAVED ADCS USING INJECTION OF RANDOM PULSES | EP13790380 | 2013-05-02 | EP2850732A4 | 2016-08-17 | ALI AHMED MOHAMED ABDELATTY |
| A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a pulsed, substantially-random signal into a plurality of channels in the ADC. After the substantially-random signal is injected, a gain correlation value is determined for each channel, which value indicates a degree of correlation between the injected substantially-random signal and an output of the respective channel. The gain correlation values are then compared to determine a degree of mismatch between the channels. At least one of the channels is calibrated as a function of the determined degree of mismatch. | ||||||
| 45 | FIELD DEVICE INCLUDING A SOFTWARE CONFIGURABLE ANALOG TO DIGITAL CONVERTER SYSTEM | EP14740788.6 | 2014-01-07 | EP2946475A1 | 2015-11-25 | MULDOWNEY, Mark, L.; WILKS, Gary; WANG, Yang |
| A method of analog to digital conversion for a field device having an analog to digital converter system (ADCS) including an ADC and a plurality of filters. An analog sensing signal is received from a sensor which measures a level of a physical parameter in a manufacturing system that runs a physical process. A level of the physical parameter is compared to reference noise data. Based on the comparing, at least one ADCS parameter is determined. The ADCS parameter is implemented to configure the ADCS. The ADCS is utilized with the ADCS parameter to generate a filtered digitized sensing signal from the analog sensing signal. | ||||||
| 46 | ANALOG FRONT END DEVICE WITH TWO-WIRE INTERFACE | EP12795181.2 | 2012-11-09 | EP2776933A1 | 2014-09-17 | QUIQUEMPOIX, Vincent |
| An analog front end (AFE) device has at least one programmable analog-to-digital converter (ADC) and a serial interface switchable to operate in a bidirectional serial interface mode and in a unidirectional two wire serial interface mode, wherein the unidirectional two wire serial interface mode only uses a clock input and a data output signal line, wherein the ADC operates in the unidirectional two wire serial interface mode synchronous with a clock supplied to the clock input. | ||||||
| 47 | Zero point correction circuit of load meter | EP06251215.7 | 2006-03-07 | EP1701146A1 | 2006-09-13 | Moriya, Hiroyuki |
The present invention relates to a zero point correction circuit for a load meter used for a press machine or the like, and more particularly to a configuration with which a zero point correction is made a plurality of times after a predetermined amount of time elapses, after press processing is performed, and a zero point correction value is set by calculating an average value of measured values. The predetermined amount of time is measured, for example, with an internal timer or the like, a sampling process is performed after the predetermined amount of time elapses, and an average value of sampled values is calculated and set as a zero point correction value, whereby an accurate zero point correction value can be obtained.
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| 48 | Pipelined A/D converter and method for correcting error in output of the same | EP05018301.1 | 2005-08-23 | EP1630964A2 | 2006-03-01 | Dosho, Shiro; Morie, Takashi; Ogita, Shinichi; Ohtani, Mitsuhiko |
Two capacitors in a variable stage are controlled from outside to function as a feedback capacitor and a sampling capacitor, respectively. With a test signal being supplied to the variable stage from an input selecting section, a stage evaluation section estimates an error in the output of the variable stage based on a difference between the digital outputs of an output correction section produced in two situations in which the functions of the two capacitors in the variable stage are switched. A correction value calculation section calculates a digital correction value for each variable stage based on the estimated error and an intermediate output of a digital calculation section. The output correction section corrects the digital output of the digital calculation section based on these digital correction values.
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| 49 | Verfahren und Anordnung zum hochauflösenden Digitalisieren eines Signales | EP85111624.4 | 1985-09-13 | EP0177803B1 | 1991-05-29 | Elmqvist, Hakan, Dr. |
| 50 | Digital to analog converter | EP82104594.5 | 1982-05-26 | EP0066251B1 | 1988-12-28 | Hareyama, Kyuichi; Shiraki, Kenji; Ryu, Kazuo |
| 51 | Digital-to-analog converter | EP82102454.4 | 1982-03-24 | EP0061199B1 | 1988-09-07 | Hotta, Masao; Maio, Kenji; Nagaishi, Hiromi |
| 52 | Method for digitising a signal with a high resolution | EP85111624 | 1985-09-13 | EP0177803A3 | 1988-08-31 | Elmqvist, Hakan, Dr. |
| 53 | DIGITAL-TO-ANALOG CONVERTER | EP82102454 | 1982-03-24 | EP0061199A3 | 1984-07-25 | HOTTA, MASAO; MAIO, KENJI; NAGAISHI, HIROMI |
| 54 | Signal transmission systems | EP79300995.2 | 1979-05-30 | EP0005999A1 | 1979-12-12 | Baron, John Robert; Coggan, Robert Keith |
This is a signal transmission system including an analogue multiplexer 11, a switched gain amplifier 15. a mode amplifier 17, a sample and hold stage 19, and an analogue to digital converter 22. Off-set errors can be precalculated and then corrected for by switching the input to the amplifiers 15 and 17 to null, and storing the output from the converter 22. and the amplified output from the amplifier 15 respectively at 'X' and 'Y' and then combining those stored off-set error signals at 46 at the input to the converter 22 during a subsequent analogue to digital conversion. |
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| 55 | 다중 채널 아날로그-디지털 변환기의 채널 응답 측정 방법 및 채널 왜곡 보상 방법 | KR1020140184472 | 2014-12-19 | KR1020160075921A | 2016-06-30 | 조치현; 이주광; 김정환 |
| 본발명에따른타임인터리빙방식의아날로그-디지털변환기의채널응답측정방법은, 제 1 주파수의제 1 신호와기준주파수의제 2 신호가혼합된신호를상기아날로그-디지털변환기에인가하고제 1 응답을측정하는단계, 제 2 주파수의제 3 신호와상기제 2 신호를혼합하여상기아날로그-디지털변환기에인가하고제 2 응답을측정하는단계, 상기제 2 신호를기준으로상기아날로그-디지털변환기의채널시퀀스를추정하는단계, 그리고상기추정된채널시퀀스, 상기제 1 내지제 2 응답을참조하여인터리빙되는복수의아날로그-디지털변환기들각각의응답특성을결정하는단계를포함한다. 또한, 상기측정된채널응압특성을참조하여샘플링된원 측정값을상기복수의채널들각각으로분리하되, 각각의채널에비어있는타임슬롯은 '0'으로채워분리신호(Ymeas)를생성하는단계, 상기채널들각각에대응하는분리신호에대한주파수영역에서의벡터회전량(E)을생성하는단계, 그리고상기채널들각각에대한응답특성(H) 및상기벡터회전량(E)을참조하여상기채널들각각의복원신호(Yreconst)를계산하는단계를포함한다. | ||||||
| 56 | 신호처리장치 및 이를 이용한 신호처리방법 | KR1020140178691 | 2014-12-11 | KR1020160071577A | 2016-06-22 | 이철승; 정형균 |
| 본발명은신호처리장치및 이를이용한신호처리방법에관한것이다. 본발명의신호처리장치는센서로부터입력된센서입력값을디지털코드로변환하여출력하는 ADC, 상기변환된디지털코드를전압출력값으로변환하여출력하는신호처리부, 전압출력값을아날로그신호로변환하여출력하는 DAC 및미리정해진테스트입력값을이용하여상기 DAC의출력특성함수를산출하고, 상기출력특성함수를이용하여제1 전압출력값의출력오차가보상된제2 전압출력값을산출하며, 상기제2 전압출력값에대응되는보상디지털코드를생성하여상기 DAC에입력하는보상부를포함하는것을특징으로한다. 본발명에의하면, DAC의출력특성함수를이용하여출력오차가보상된전압출력값의보상디지털신호를생성함으로써, DAC의게인또는오프셋을보상하기위한별도의회로를구성하지않아도되므로제조비용을절감시킬수 있고, 동시에출력오차를크게줄일수 있는장점이있다. | ||||||
| 57 | 아날로그-디지털 변환기의 테스트 장치 및 테스트 방법 | KR1020140029193 | 2014-03-12 | KR101542190B1 | 2015-08-11 | 강성호; 손현욱 |
| 본 발명은 아날로그-디지털 변환기의 테스트 장치 및 방법에 관한 것으로, 아날로그-디지털 변환기의 테스트 장치는, 직렬 연결되고, 입력 신호에 대응하는 디지털 신호들을 순차적으로 출력하는 복수의 스테이지를 포함하는 아날로그-디지털 변환기의 테스트 장치로서, 복수의 스테이지 각각으로부터 출력되는 디지털 신호의 빈도 수를 비트 값 별로 누적하여 복수의 스테이지 각각에 대해 서브 히스토그램 데이터를 생성하는 히스토그램 데이터 생성부; 및 복수의 스테이지 각각에 대하여 생성된 서브 히스토그램 데이터에 기초하여, 복수의 스테이지 각각의 이상 여부를 판단하는 히스토그램 데이터 분석부를 포함한다. | ||||||
| 58 | 커패시터의 미스매치 모델링 방법 | KR1020080127705 | 2008-12-16 | KR1020100069115A | 2010-06-24 | 최정현 |
| PURPOSE: A mismatch modeling method of a capacitor is provided to measure mismatch of an MIM(Metal-Insulator-Metal) capacitor changing each rate or size, thereby modeling a rate and side of the capacitor according to a property of an analog circuit. CONSTITUTION: An analog circuit having a capacitor changing a rate or size is prepared and measures each mismatch value(304). A modeling parameter calculates a mismatch model according to the mismatch value and the rate or size of the capacitor and is extracted. A real capacitor mismatch value is calculated by applying the modeling parameter and a rate and size of the real capacitor for modeling to the mismatch model(308). | ||||||
| 59 | Self-adaptive analog-to-digital converter | US15700957 | 2017-09-11 | US09923569B1 | 2018-03-20 | Baozhen Chen; Lalinda D. Fernando; Frank M. Yaul |
| A self-adaptive SAR ADC techniques that can increase speed and/or decrease its power consumption. In some example approaches, one or more bits from a conversion of a previous sample of an analog input signal can be preloaded onto a DAC circuit of the ADC. If the preloaded bits are determined to be acceptable, bit trials on the current sample can be performed to determine the remaining bits. If not acceptable, the ADC can discard the preloaded bits and perform bit trials on all of the bits. The self-adaptive SAR ADC can include a control loop to adjust, e.g., increase or decrease, the number of bits that are preloaded in a subsequent bit trial using historical data. | ||||||
| 60 | FRACTIONAL DIVIDER USING A CALIBRATED DIGITAL-TO-TIME CONVERTER | US15479499 | 2017-04-05 | US20170364034A1 | 2017-12-21 | Song Gao; Brian Buell; Katherine T. Blinick |
| An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal. | ||||||
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