| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | AN ANALOG-TO-DIGITAL CONVERSION CIRCUIT, A PIXEL COMPENSATION CIRCUIT FOR DISPLAY PANEL, AND METHODS THEREOF | US15766085 | 2017-09-20 | US20190123761A1 | 2019-04-25 | Chen Song; Song Meng; Danna Song; Zhongyuan Wu |
| The present application discloses an analog-to-digital conversion (ADC) circuit. The circuit includes an integral circuit including an operational amplifier and an integral capacitor. The circuit further includes a comparator and a timer. The operational amplifier includes a positive input terminal configured to receive a first voltage, a negative input terminal coupled to a signal-collection line configured to collect an analog current signal, and an output terminal configured to output a first output signal. The comparator is configured to compare the first output signal with a second voltage to generate a second output signal to the timer. The timer is configured to start a timing operation when the operational amplifier receives the analog current signal and end the timing operation when the second output signal changes. A binary data resulted from the timing operation characterizes a digital signal corresponding to the analog current signal. | ||||||
| 142 | DEVICE AND METHOD FOR CORRECTING ERROR ESTIMATION OF ANALOG-TO-DIGITAL CONVERTER | US15742835 | 2015-08-20 | US20180358976A1 | 2018-12-13 | Jie PU; Gangyi HU; Xiaofeng SHEN; Xueliang XU; Dongbing FU; Ruitao ZHANG; Youhua WANG; Yuxin WANG; Guangbing CHEN; Ruzhang LI |
| A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimation correction. | ||||||
| 143 | A/D CONVERSION DEVICE | US15752096 | 2015-11-11 | US20180241411A1 | 2018-08-23 | Yusuke KOBAYASHI; Takayasu NARUKAWA; Masaya TSUNEOKA; Masayuki FUNAKOSHI; Norihiro YAMAGUCHI; Takahiro OKANOUE |
| A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode. | ||||||
| 144 | Wideband Nyquist VCO-based analog-to-digital converter | US15507704 | 2015-09-02 | US10009038B2 | 2018-06-26 | Shuo-Wei Chen |
| An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator. | ||||||
| 145 | Fractional divider using a calibrated digital-to-time converter | US15479499 | 2017-04-05 | US09897976B2 | 2018-02-20 | Song Gao; Brian Buell; Katherine T. Blinick |
| An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal. | ||||||
| 146 | ANALOG/DIGITAL CONVERSION CIRCUIT | US15117246 | 2015-05-18 | US20160352350A1 | 2016-12-01 | Yukihiko TANIZAWA |
| An A/D conversion circuit includes: first/second pulse circulation circuits delaying an input signal and circulating a pulse signal; a circulation number difference measurement section outputting a difference between circulation time numbers of the pulse signal through the first/second pulse circulation circuits; a conversion control circuit outputting the difference as A/D conversion data when outputting a conversion data output processing signal; and a signal ratio change circuit: outputting, from a first output terminal, a voltage calculated by adding the reference voltage and a voltage obtained by multiplying a differential voltage, obtained by subtracting the reference voltage from the analog input voltage, by a first proportional coefficient; and outputting, from a second output terminal, a voltage calculated by subtracting, from the reference voltage, a voltage obtained by multiplying the differential voltage by a second proportional coefficient. The first/second pulse circulation circuits receive power source voltage supply from the first/second output terminals and a ground line. | ||||||
| 147 | Systems and methods of element scrambling for compensation and calibration of analog-to-digital converter feedback | US14617376 | 2015-02-09 | US09407279B2 | 2016-08-02 | John L. Melanson; Jaimin Mehta; Stephen T. Hodapp |
| An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal. | ||||||
| 148 | Analog-digital converter | US14749352 | 2015-06-24 | US09300312B2 | 2016-03-29 | Lukas Kull; Thomas H. Toifl |
| An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch. | ||||||
| 149 | SYSTEMS AND METHODS OF ELEMENT SCRAMBLING FOR COMPENSATION AND CALIBRATION OF ANALOG-TO-DIGITAL CONVERTER FEEDBACK | US14617376 | 2015-02-09 | US20160006448A1 | 2016-01-07 | John L. Melanson; Jaimin Mehta; Stephen T. Hodapp |
| An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal. | ||||||
| 150 | Self-calibrating VCO-based analog-to-digital converter and method thereof | US14291441 | 2014-05-30 | US09214951B1 | 2015-12-15 | Chia-Liang (Leon) Lin |
| A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal. | ||||||
| 151 | SENSOR SIGNAL PROCESSING APPARATUS AND SENSOR APPARATUS | US14758613 | 2014-01-21 | US20150358027A1 | 2015-12-10 | Yukihiko TANIZAWA |
| In a sensor signal processing apparatus, a control unit executes at least one of a temperature measurement process and a calculation process in parallel with a signal conversion process. In the temperature measurement process, the control unit causes a second A/D converter to execute the A/D conversion of a temperature signal. In the calculation process, the control unit calculates an offset and a conversion gain of a first A/D converter base on an A/D conversion value output from the second A/D converter and pre-prepared temperature characteristic data of a physical quantity sensor. In the signal conversion process, the control unit sets the calculated offset and the calculated conversion gain to the first A/D converter, and causes the first A/D converter to execute the A/D conversion of the sensor signal. | ||||||
| 152 | Analog-digital converter | US14625016 | 2015-02-18 | US09191018B2 | 2015-11-17 | Lukas Kull; Thomas H. Toifl |
| An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch. | ||||||
| 153 | ANALOG-DIGITAL CONVERTER | US14625016 | 2015-02-18 | US20150244383A1 | 2015-08-27 | Lukas Kull; Thomas H. Toifl |
| An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch. | ||||||
| 154 | Communication device and method capable of power calibration | US14297230 | 2014-06-05 | US09030343B2 | 2015-05-12 | Yu-Cheng Chen; Tsung-Hsuan Lee; Chung-Yao Chang |
| The present invention discloses a communication device and a communication method capable of power calibration. Said communication device comprises: a digital circuit to provide a digital output signal; a detection circuit to perform a predetermined detection and generate a detection result; a control circuit to generate a digital-end and an analog-end gain adjustment signals according to the detection result; a digital-end gain adjustment circuit to adjust the gain of the digital output signal according to the digital-end gain adjustment signal and generate a digital gain-adjusted output signal; a digital-to-analog converter to generate an analog output signal according to the digital gain-adjusted output signal; and an analog circuit to adjust the gain of the analog output signal according to the analog-end gain adjustment signal and generate an analog gain-adjusted output signal, wherein the detection circuit is operable to detect the influence caused by a peripheral factor to the analog circuit. | ||||||
| 155 | Artifact-corrected time-interleaved ADC | US13937074 | 2013-07-08 | US08957798B1 | 2015-02-17 | Fredric J. Harris |
| An artifact-corrected time-interleaved analog-to-digital converter (ADC) for communications signals offers a significant increase in the available sample rate of ADCs by correcting timing and gain mismatches between ADC channels. These mismatches are corrected in the digital data section of a two-channel TI-ADC for band-pass input signals. This is a realistic communications system scenario as modern system designs lean towards having the ADC interface with the intermediate frequency (IF) signal in the analog section of a digital receiver rather than in the DC centered, analog down converted, in-phase and quadrature pair. | ||||||
| 156 | Communication device and method capable of power calibration | US14297230 | 2014-06-05 | US20150042497A1 | 2015-02-12 | YU-CHENG CHEN; TSUNG-HSUAN LEE; CHUNG-YAO CHANG |
| The present invention discloses a communication device and a communication method capable of power calibration. Said communication device comprises: a digital circuit to provide a digital output signal; a detection circuit to perform a predetermined detection and generate a detection result; a control circuit to generate a digital-end and an analog-end gain adjustment signals according to the detection result; a digital-end gain adjustment circuit to adjust the gain of the digital output signal according to the digital-end gain adjustment signal and generate a digital gain-adjusted output signal; a digital-to-analog converter to generate an analog output signal according to the digital gain-adjusted output signal; and an analog circuit to adjust the gain of the analog output signal according to the analog-end gain adjustment signal and generate an analog gain-adjusted output signal, wherein the detection circuit is operable to detect the influence caused by a peripheral factor to the analog circuit. | ||||||
| 157 | FIELD DEVICE INCLUDING A SOFTWARE CONFIGURABLE ANALOG TO DIGITAL CONVERTER SYSTEM | US13744106 | 2013-01-17 | US20140200850A1 | 2014-07-17 | MARK L. MULDOWNEY; GARY WILKS; YANG WANG |
| A method of analog to digital conversion for a field device having an analog to digital converter system (ADCS) including an ADC and a plurality of filters. An analog sensing signal is received from a sensor which measures a level of a physical parameter in a manufacturing system that runs a physical process. A level of the physical parameter is compared to reference noise data. Based on the comparing, at least one ADCS parameter is determined. The ADCS parameter is implemented to configure the ADCS. The ADCS is utilized with the ADCS parameter to generate a filtered digitized sensing signal from the analog sensing signal. | ||||||
| 158 | APPARATUS, SYSTEMS AND METHODS FOR FOR DIGITAL TESTING OF ADC/DAC COMBINATION | US13992765 | 2011-12-07 | US20140191890A1 | 2014-07-10 | Stephen J. Spinks; Andrew Talbot; Colin Mair |
| A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches. | ||||||
| 159 | Analog front end device with two-wire interface | US13671903 | 2012-11-08 | US08742968B2 | 2014-06-03 | Vincent Quiquempoix |
| An analog front end (AFE) device has at least one programmable analog-to-digital converter (ADC) and a serial interface switchable to operate in a bidirectional serial interface mode and in a unidirectional two wire serial interface mode, wherein the unidirectional two wire serial interface mode only uses a clock input and a data output signal line, wherein the ADC operates in the unidirectional two wire serial interface mode synchronous with a clock supplied to the clock input. | ||||||
| 160 | TIME-TO-DIGITAL CONVERTER WITH BUILT-IN SELF TEST | US12684771 | 2010-01-08 | US20110169673A1 | 2011-07-14 | Stephan Henzler |
| Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices. | ||||||
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