| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | System and method for timing calibration of time-interleaved data converters | US11120698 | 2005-05-03 | US07148828B2 | 2006-12-12 | Andrew D. Fernandez; Vamsi K. Srikantam; Robert M. R. Neff; Kenneth D. Poulton |
| A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample. | ||||||
| 162 | SYSTEM AND METHOD FOR TIMING CALIBRATION OF TIME-INTERLEAVED DATA CONVERTERS | US11120698 | 2005-05-03 | US20060250288A1 | 2006-11-09 | Andrew Fernandez; Vamsi Srikantam; Robert Neff; Kenneth Poulton |
| A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample. | ||||||
| 163 | Method of determining measuring time for an analog-digital converter | US09891788 | 2001-06-26 | US06559782B2 | 2003-05-06 | Tomonobu Hiramatsu; Shinichi Tanida |
| In order to shorten the measuring time of an analog-digital converter for measuring very small currents with its resolution unchanged, a method of determining the measuring time for the analog-digital converter which comprises the steps of preliminarily measuring current to be measured, determining a voltage range and a current range used for measurement, and determining the measuring time for an analog-digital converter for current measurement on the basis of the determined voltage and current ranges, and the measured current value is provided. | ||||||
| 164 | Two-step parallel analog to digital converter | US237757 | 1988-08-29 | US4875048A | 1989-10-17 | Toshihiko Shimizu; Masao Hotta; Kenji Maio |
| In a two-step parallel analog to digital converter of the type in which a first flash-type A/D converter determines the upper significant bits of a digital signal output having a desired number of bits and after a quantizing error of the first flash-type A/D converter has been determined from the difference between a value obtained by reconverting the upper significant bits to an analog value and the input analog value a second flash-type A/D converter subjects the quantizing error to A/D conversion to determine a digital output of the remaining lower significant bits, a gain correcting circuit is additionally provided to automatically establish a gain of a D/A converter for reconverting the upper significant bits to an analog value on the basis of a reference voltage applied to the first flash-type A/D converter. Moreover, a reference voltage generating circuit is additionally provided to establish upper and lower reference voltages of a second flash-type A/D converter for determining lower significant bits on the basis of the step voltage of the DAC output. | ||||||
| 165 | Architecture for high speed analog to digital converters | US111764 | 1987-10-23 | US4862171A | 1989-08-29 | William P. Evans |
| A very high speed, high resolution analog to digital converter is detained including a subrange architecture, with the main range A/D including a digital to analog portion for producing an analog signal which can be summed with an amplified input analog signal. The summed analog signal is directed through a unity gain buffer to the subrange analog to digital converter, with the buffer isolating the high input capacitance of the subrange A/D from the summing node. The main range A/D provides a binary coded digital signal which approximates the input analog signal and which defines the most significant bits (MSB) of the digital output. The least significant bits (LSB) are had from the subrange A/D which provides at least one more bit than the number of MSB to provide overlap for forming the combined digital output signal. | ||||||
| 166 | Large dynamic range analog to digital converter | US95500 | 1987-09-11 | US4843395A | 1989-06-27 | Arthur L. Morse |
| An analog-to-digital converter system for converting an input analog signal having a wide dynamic range to a digital output has a non-linear function generator for compressing the wide dynamic range input signal to a reduced dynamic range signal, an analog-to-digital converter of limited dynamic range for converting the reduced dynamic range signal to a digitally formatted signal, and a conversion memory for providing a digital value corresponding to the value of the wide range analog input. The digitally formatted signal addresses a word within the conversion memory, the word so addressed containing a digital value corresponding to the magnitude of the analog input signal. Each word of the conversion memory has a sufficient number of bits for expressing the desired dynamic range of the input signal. In one embodiment of the invention a digital counter and a digital to analog converter provides for calibrating the system, the output of the counter being stored in the conversion memory which, in this embodiment, is composed of RAM data storage elements. | ||||||
| 167 | Analog-to-digital converter | US18034 | 1987-02-24 | US4823129A | 1989-04-18 | John H. Nelson |
| A floating point analog-to-digital converter providing a variety of analog representations of the analog signal value to be converted, each of which representations is converted to a digital equivalent from which the floating point result is obtained. | ||||||
| 168 | Analog to digital conversion | US92115 | 1987-09-02 | US4812848A | 1989-03-14 | John J. Fry |
| A method and apparatus of converting analog voltage signals to digital frequency signals comprises a voltage to frequency converter having an output which produces pulse trains that are proportional to the voltage level of an analog voltage signal applied to the converter. A microprocessor is connected to the converter for sampling the pulse trains during a fixed sampling period. The microprocessor detects the leading edges of the first and last pulse in the pulse train, stores the occurrence time for the two leading edges and then subtracts the occurrence times to calculate the duration time for all the pulses in the sample period between the leading edges of the first and last pulses. A counter counts the number of pulses between the first and last pulse, and a calculation is made dividing the number of pulses by the time duration to yield an accurate measurement of the frequency for the pulse train. A precision reference voltage along with a plurality of analog voltage signals to be measured, is applied to the plural inputs of a multiplexer. The output of the multiplexer is then amplified and a level shifted before it is applied to the converter. The microprocessor drives the multiplexer to sequentially apply signals to the converter. During each complete cycle of the multiplexer the microprocessor receives a pulse train corresponding to the reference voltage signal. A stored frequency for that reference pulse train is then compared to the actual frequency which results from the reference voltage to determine whether any shifts in ambient conditions have caused shifts in the output of the converter. This shift is interpreted as being caused by changes in ambient condition and is applied equally to all other measured frequencies. In this way, inexpensive components can be used while still maintaining accuracy for a wide range of ambient conditions. | ||||||
| 169 | Flash A/D Converter | US45996 | 1987-05-04 | US4794374A | 1988-12-27 | Yukio Koike |
| An A/D converter comprises a resistor ladder connected between first and second reference potentials so that each connection tap provides a different divided reference potential. A plurality of first switches are each connected at their one end to one connection tap of the resistor ladder and at their other end to a corresponding number of common connection nodes. Also, a plurality of second switches are each connected at their one end commonly to an input for an analog voltage signal and at their other end to the corresponding common connection nodes. Each of the nodes is connected through one coupling capacitor to one amplifier having adapted to generate an output signal representative of whether the voltage of the input signal is higher or lower than a voltage appearing at the above mentioned one connection tap of the resistor ladder. Each of the amplifier has a third switch connected between the input and the output of the amplifier, and an encoder is connected to the output of each amplifier so as to generate an digital signal corresponding to the input analog signal. Each of the common connection nodes are connected through an associated fourth switch to a bias voltage source. In a pre-calibration period proceeding to a calibration period, the third and fourth switches are closed so that the respective common connection nodes are forcedly and rapidly charged or discharged through the bias voltage source. | ||||||
| 170 | Flash A/D converter using capacitor arrays | US45349 | 1987-05-01 | US4742330A | 1988-05-03 | Joey Doernberg; Paul R. Gray; David A. Hodges |
| A flash ADC utilizes parallel weighted capacitive arrays and a resistor string to provide reference voltage intervals and an encoder for indicating the reference voltage interval wherein an input voltage lies. For an embodiment having N branches, the reference voltage intervals are subdivided into N sub-intervals and each succeeding clock cycle. | ||||||
| 171 | Self-calibrating adaptive ranging apparatus and method | US526663 | 1983-08-26 | US4616329A | 1986-10-07 | David Abrams; Raul Curbelo; R. Brough Turner |
| Apparatus and method for calibrating an adaptive ranging A/D converter wherein a noise having known statistical properties is deliberately superposed on the reference DC signals used to calibrate the gain-ranging amplifier. The amplitude of the noise is chosen to be greater than at least one, and preferably several, least significant digits of the A/D converter at the lowest anticipated gain, yet preferably less than half the counting range of the converter at the highest gain. The reference DC signal levels are chosen to be spaced from the minimum and maximum count of the A/D at the lowest and highest anticipated gains by better than half the noise amplitude. A time average of a series of measurements of the noisy reference signals as amplified and digitized by the system are obtained. The statistical properties of the noise generator permits the system output corresponding to the reference signals to be determined to a greater accuracy than the resolution of the A/D, thereby allowing the gain and offset of the gain-ranging amplifier to be determined with greater precision than is possible by injecting noiseless DC signals alone. | ||||||
| 172 | Trimmable resistive scaling network suitable for digital to analog converters | US351501 | 1982-02-23 | US4542368A | 1985-09-17 | William J. Lillis |
| A trimmable resistive scaling network suitable for use in digital-to-analog converters or the like. At least two trimmable resistors with low order integral relative values provide for either scaling up or scaling down with high accuracy. | ||||||
| 173 | Microprocessor supervised analog-to-digital converter | US386428 | 1982-06-08 | US4490713A | 1984-12-25 | Andrij Mrozowski; Paul R. Prazak |
| An analog-to-digital converter which is supervised by a microprocessor and includes means for digitally compensating for initial gain and offset errors and gain and offset drift errors due to temperature variations. An analog input voltage is applied to a first analog-to-digital converter, the output of which is both stored in the microprocessor and applied to a linear digital-to-analog converter. The output of the linear converter is summed with the original analog input voltage and the difference applied to the conversion apparatus as an unknown input signal. This process is continued to achieve a desired resolution. The output of a differential temperature sensor is similarly processed to determine the proper amount of compensation for gain and offset drift. The microprocessor provides both control and computation capabilities. | ||||||
| 174 | System for interfacing an encoder to a microcomputer | US386152 | 1982-06-07 | US4461944A | 1984-07-24 | Robert K. Cohen |
| Data generated by an encoder with phase quadrature outputs, for instance a displacement transducer in a resistance spot welder control system, is read out of the interface to the computer in a format compatible with computer languages. The quadrature signals are converted to pulses representing positive and negative unit changes of displacement, and fed to an up-down counter which has signed two's complement values at its output. The most recent displacement data is read out while the counter continuously tracks the encoder. | ||||||
| 175 | Statistically adaptive analog to digital converter | US294273 | 1981-08-19 | US4395732A | 1983-07-26 | Eric L. Upton |
| An improvement in an analog-to-digital converter wherein a series string of capacitors is utilized to generate reference voltages for the comparators of the converter. The digitized output of the converter is then used to control a predetermined timed discharge from a selected one of the series string of capacitors. The converter, as described, may be used in a video system as an adaptive contrast enhancement mechanism. | ||||||
| 176 | Analog to digital converter without zero drift | US262555 | 1981-05-11 | US4390864A | 1983-06-28 | A. Newman Ormond |
| The conversion is effected by adding equal and opposite reference voltages to the analog signal to provide two first output voltage levels. The voltage difference between these levels is converted into a first given number of pulses. The polarity of the analog signal is then reversed during the second half of the cycle so as to be subtracted from the reference voltages for providing two second output voltage levels. The voltage difference between these levels is converted into a second given number of pulses. A function of the first and second number of pulses provides a numerical count directly proportional to the analog signal and because of the bipolar operation; that is, the switching of the polarity of the analog input signal, all zero drift is eliminated. A second conversion can be made with the reference voltages reversed in polarity and the analog voltage removed, the resulting numerical count being used in conjunction with the first obtained numerical count from the first conversion to provide a digital read-out which is free, not only from zero drift but also from span drift. | ||||||
| 177 | Calibration apparatus for analog-to-digital converter | US232481 | 1981-02-09 | US4364027A | 1982-12-14 | Rikichi Murooka |
| A calibration apparatus for analog-to-digital converter or transient recorder including both analog and digital sections is disclosed. A built-in calibrator automatically calibrates the gain and DC level of the entire system to substantially the same accuracy as that of the digital section, thereby avoiding relatively large errors of the analog section. The amplitude or gain calibration is always performed over the full range of the digitizer used in the digital section. | ||||||
| 178 | Dynamically calibrated successive ranging A/D conversion system and D/A converter for use therein | US176625 | 1980-08-11 | US4342983A | 1982-08-03 | Benjamin F. Weigand; John W. Frech |
| One aspect of the present invention provides for apparatus for dynamically calibrating the internal offsets of the various range conversion paths as well as the overall offset of a successive ranging A/D conversion system over time and temperature variations. More specifically, this apparatus includes at least two time-gated integrator circuits which are respectively coupled to each of the range conversion paths of the conversion system. Each integrator is operative at predetermined times to generate a corresponding compensating signal in response to the digital code of one of the path conversion results. The compensating signals are used to dynamically calibrate the internal and overall offsets of the A/D conversion system. Further included in the apparatus are switching devices disposed at the input and feedback paths of the system to provide for appropriate system conditions at the predetermined calibration times. Another aspect of the present invention is directed to a D/A converter which may be disposed in at least one of the feedback paths of the system. The D/A converter includes apparatus for self-compensating the conversion inaccuracies thereof. An additional aspect of the present invention is directed to extending the resolution of the D/A converter to at least one additional bit, thus doubling the resolution thereof. | ||||||
| 179 | Autocalibration of compressed A/D converter | US11822 | 1979-02-13 | US4338589A | 1982-07-06 | Steven J. Engel; Richard E. Marsh; Robert P. Rhodes |
| An analog-to-digital converter system is disclosed in which the amplitude of the signal is compressed by means including a logging means prior to an analog-to-digital converter. Reference signals of known values are applied to the logging means and their values at the output of the converter are used to determine a linearity factor which is applied to a multiplier coupled to the output of the converter. The amplitude of one of the reference signals at the output of the multiplier is compared with what it should be and the difference is added by an adder at the output of the multiplier. | ||||||
| 180 | Error correction in recirculating remainder analog-to-digital converters | US84767 | 1979-10-15 | US4315253A | 1982-02-09 | Hulbert T. Tytus |
| A recirculating remainder analog-to-digital conversion method and apparatus are disclosed for converting an analog signal into a digitally encoded signal representing the analog signal as two or more digits in a selected number base. Conversion is based on employing two gain factors, one dependent on the digital code used for encoding digits, such as a binary code, and the other dependent on the selected number base for the digits, such as decimal, and by selectively amplifying by the gain factors in a predetermined sequence for producing the signals that are recirculated during conversion of the analog signal into the digitally encoded signal. A method and apparatus are also disclosed for nulling errors in recirculating remainder converters introduced by operation of the converter circuitry by transferring signals through the circuitry once at one polarity and again at the opposite polarity during conversion of the analog signal into the digitally encoded signal. | ||||||
QQ群二维码
意见反馈
意见反馈