| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | Physical quantity sensor device and method of adjusting physical quantity sensor device | US14642457 | 2015-03-09 | US10126145B2 | 2018-11-13 | Mutsuo Nishikawa; Katsuyuki Uematsu; Kazuhiro Matsunami |
| An analog signal is supplied to a first conversion section of a physical quantity sensor device, converted to digital, and set to be an initial output value of the first conversion section. Adjustment information for the first conversion section is calculated based on the error between the initial output value and a target output value of the first conversion section. Before an initial output value of a physical quantity sensor is measured for calculating initial setting information of a physical quantity sensor device, the first conversion section is adjusted based on the adjustment information. Also, a digital signal is supplied to a second conversion section of the physical quantity sensor device, converted to analog, and set to be an initial output value of the second conversion section. The second conversion section is adjusted based on adjustment information for the second conversion section. | ||||||
| 102 | VARIABLE GAIN AMPLIFIER UTILIZING POSITIVE FEEDBACK AND TIME-DOMAIN CALIBRATION | US15803081 | 2017-11-03 | US20180309408A1 | 2018-10-25 | Nan Sun; Miguel Gandara |
| A variable gain amplifier utilizing positive feedback and time-domain calibration includes an integration phase and a regeneration phase. A current source provides a bias current that increases linearity in the integration phase and reduces common-mode voltage dependence. The circuit includes a timing control loop, wherein a variable gain of a residue amplifier is proportional to a first time that a timing control loop signal is kept high, as determined by an on or off status of respectively paired inverter assemblies each having an input voltage determined by an amplifier output voltage during the regeneration phase. A strong-arm latch structure acts as a positive feedback latch until the first time is de-asserted. | ||||||
| 103 | Optical sensor arrangement and method for light sensing | US14493219 | 2014-09-22 | US10072976B2 | 2018-09-11 | Gonggui Xu |
| An optical sensor arrangement (10) comprises a light sensor (11), a current source (41), an analog-to-digital converter (12) and a switch (44) which selectively couples the light sensor (11) or the current source (41) to an input (14) of the analog-to-digital converter (12). | ||||||
| 104 | Multiplexer circuit for a digital to analog converter | US15684737 | 2017-08-23 | US10069508B1 | 2018-09-04 | Jiawen Zhang; Adesh Garg; Ali Nazemi; Jun Cao |
| Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data. | ||||||
| 105 | On-Board Control Device, On-Board Integrated Circuit | US15569152 | 2016-07-06 | US20180141566A1 | 2018-05-24 | Youichirou KOBAYASHI; Masahito SONEHARA |
| Provided is a semiconductor integrated circuit which can continuously and stably generate an output value even after shipment and a vehicle-mounted control device using the semiconductor integrated circuit. The present invention includes a reference signal generation unit for outputting a reference signal, and detects the operation state of a semiconductor circuit on the basis of a difference between output values from the semiconductor circuit corresponding to the reference signals output at two different time points by the reference signal generation unit. | ||||||
| 106 | WIDEBAND NYQUIST VCO-BASED ANALOG-TO-DIGITAL CONVERTER | US15507704 | 2015-09-02 | US20170310334A1 | 2017-10-26 | Shuo-Wei Chen |
| An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator. | ||||||
| 107 | Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration | US15141498 | 2016-04-28 | US09685969B1 | 2017-06-20 | Adesh Garg; Ali Nazemi; Anand Jitendra Vasani; Hyo Gyuem Rhew; Jiawen Zhang; Jun Cao; Meisam Honarvar Nazari; Afshin Momtaz; Tamer Ali |
| A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture. | ||||||
| 108 | Third order harmonic distortion correction circuit using a reference analog digital converter | US15008733 | 2016-01-28 | US09461661B1 | 2016-10-04 | Lukas Kull; Danny Chen-Hsien Luu; Thomas H. Toifl |
| A linear reference analog to digital converter (ADC) network may include a first ADC operatively connected to a first sample and hold circuit. The linear reference ADC network may be configured to receive an input signal from the first sample and hold circuit and sample the input signal with a harmonic distortion. The linear reference ADC network may further include a reference ADC operatively connected to a second sample and hold circuit and configured to receive the input signal and sample the input signal with a second harmonic distortion. The linear reference ADC network may further include a combining module operatively connected to the first ADC and the reference ADC, the combining module configured to equalize a linearity of an output of the first ADC to a linearity of an output of the reference ADC, and output a combined output signal, and a circuit configured to output a calibrated output signal having calibrated harmonic distortion content. | ||||||
| 109 | Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for generating a processed oscillator signal, an apparatus for generating a processed oscillator signal, and software-related implementations | US14832342 | 2015-08-21 | US09438259B2 | 2016-09-06 | Stefan Tertinek; Peter Preyler; Thomas Mayer |
| A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique. | ||||||
| 110 | CIRCUIT CALIBRATING METHOD AND CIRCUIT CALIBRATING SYSTEM | US14753036 | 2015-06-29 | US20160173116A1 | 2016-06-16 | Hsiang-Wei Hwang; Yung-Hung Chen; Han-Chi Liu |
| A circuit calibrating method, applied to an ACS generating circuit, which comprises a plurality of ACS generating units and activates the ACS generating unit corresponding to different DCCs to generate difference ACSs. The circuit calibrating method comprises: (a) determining which one of the ACSs has a large difference from an ideal value thereof; (b) adjusting a number of the ACS generating units, which are activated by a DCC corresponding to the ACS acquired in the step (a), or a next stage of the DCC corresponding to the ACS acquired in the step (a); and (c) generating the ACS to a target circuit, according to the number of the ACS generating circuits adjusted in the step (b). | ||||||
| 111 | Sensor signal processing apparatus and sensor apparatus | US14758613 | 2014-01-21 | US09350370B2 | 2016-05-24 | Yukihiko Tanizawa |
| In a sensor signal processing apparatus, a control unit executes at least one of a temperature measurement process and a calculation process in parallel with a signal conversion process. In the temperature measurement process, the control unit causes a second A/D converter to execute the A/D conversion of a temperature signal. In the calculation process, the control unit calculates an offset and a conversion gain of a first A/D converter base on an A/D conversion value output from the second A/D converter and pre-prepared temperature characteristic data of a physical quantity sensor. In the signal conversion process, the control unit sets the calculated offset and the calculated conversion gain to the first A/D converter, and causes the first A/D converter to execute the A/D conversion of the sensor signal. | ||||||
| 112 | CALIBRATION IN MULTIPLE SLOPE COLUMN PARALLEL ANALOG-TO-DIGITAL CONVERSION FOR IMAGE SENSORS | US14573978 | 2014-12-17 | US20150103220A1 | 2015-04-16 | Zheng Yang; Guangbin Zhang; Yuanbao Gu |
| An apparatus includes analog-to-digital (A/D) conversion circuitry coupled to a pixel array. The A/D conversion circuitry includes a voltage ramp generator and a set of column A/D conversion circuits. The voltage ramp generator generates a single slope voltage ramp in a first state and a multiple slope voltage ramp in a second state. The set of column A/D conversion circuits is coupled with the voltage ramp generator. The apparatus further includes calibration circuitry coupled with the set of column A/D conversion circuits and operable to determine digital calibration data to adjust digital image data. The calibration circuitry provides analog calibration data that spans a calibration range to the set of column A/D conversion circuits instead of the analog image data from the pixel array being provided to the set of column A/D conversion circuits. | ||||||
| 113 | CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY | US14025330 | 2013-09-12 | US20150070199A1 | 2015-03-12 | Ian Juso DEDIC; Saul Darzy; Gavin Lambertus Allen |
| A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring. | ||||||
| 114 | Analog-to-digital converter and method of converting an analog signal to a digital signal | US14194675 | 2014-03-01 | US08928515B1 | 2015-01-06 | Desheng Hu; Dawei Guo |
| An analog-to-digital converter (ADC) comprises a sample/hold (S/H) unit, a digital-to-analog converter (DAC), a comparing unit, and a control unit. The S/H unit samples a first analog signal. The control unit comprises a compensating unit. The compensating unit receives an indication signal, and compensates a current bit and all its less significant bits, such that the sum of the current bit and all its less significant bits approximates a bit weight of the current bit, when the indication signal indicates that the comparison result cannot be determined. The compensating unit then outputs the compensated current bit and all its less significant bits together with more significant bits of the current bit. | ||||||
| 115 | System and method of generating external parameter value for separately excited motor controller | US13165987 | 2011-06-22 | US08868365B2 | 2014-10-21 | Rijun Huang; Yulin Su; Ben Cai; Yanzhang Ye |
| A system and a method of generating an external parameter value for a separately excited motor controller are disclosed, the system including: a digital signal processor to convert a received analog electrical signal into a digital signal and to scale the digital signal, so as to generate a parameter value in conformity with a data format of the system; an external parameter generating module to adjust the parameter value with a calibration coefficient to obtain the external parameter value; the calibration coefficient being generated by a calibration coefficient generating module and being pre-stored in a calibration coefficient storing module; and a calibration coefficient generating module to read the parameter value generated by the digital signal processor and obtain an actual measuring value as a reference parameter value, to calculate a difference value between the parameter value from the digital signal processor and the reference parameter value, and to generate the calibration coefficient from a ratio of the reference parameter value to the parameter value obtained from the digital signal processor if the difference value exceeds a preset value. | ||||||
| 116 | CALIBRATION IN MULTIPLE SLOPE COLUMN PARALLEL ANALOG-TO-DIGITAL CONVERSION FOR IMAGE SENSORS | US14257832 | 2014-04-21 | US20140226050A1 | 2014-08-14 | Zheng Yang; Guangbin Zhang; Yuanbao Gu |
| A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed. | ||||||
| 117 | High-speed successive-approximation-register analog-to-digital converter and method thereof | US13706600 | 2012-12-06 | US08754798B2 | 2014-06-17 | Chia-Liang Lin |
| In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data. | ||||||
| 118 | Asynchronous analog-to-digital converter having rate control | US13599539 | 2012-08-30 | US08754797B2 | 2014-06-17 | Venugopal Gopinathan; Udayan Dasgupta; Ganesan Thiagarajan |
| An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal. | ||||||
| 119 | Calibration in multiple slope column parallel analog-to-digital conversion for image sensors | US13423976 | 2012-03-19 | US08730081B2 | 2014-05-20 | Zheng Yang; Guangbin Zhang; Yuanbao Gu |
| A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed. | ||||||
| 120 | METHOD FOR VERIFYING DIGITAL TO ANALOG CONVERTER DESIGN | US13965201 | 2013-08-13 | US20140115549A1 | 2014-04-24 | Cheng Wang; Chao Liang; Geng Zhong |
| A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance. | ||||||
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