子分类：
- H03M1/001： .{模拟/数字/模拟的转换}
- H03M1/002： .{节约能量的方法}
- H03M1/004： .{可重构模拟/数字或数字/模拟转换器(H03M1/02优先)}
- H03M1/02： .可逆模/数转换器
- H03M1/04： .应用随机技术的
- H03M1/06： .连续地补偿或防止物理参数有害影响(周期性地,例如.通过使用多个存储修正值的入H03M1/10)
- H03M1/10： .校正或测试
- H03M1/12： .模/数转换器(H03M1/001至H03M1/004且H03M1/02至H03M1/10优先)
- H03M1/66： .数/模转换器(H03M1/001至H03M1/004且H03M1/02至H03M1/10优先)
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 281 | Semiconductor integrated circuit device and data processing system | JP2012240110 | 2012-10-31 | JP2013179568A | 2013-09-09 | KAWAKAMI FUMIKI; YADA NAOKI; TSUNAKAWA HIROYUKI |
| PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and a data processing system that can A/D-convert a plurality of externally input analog signals in an arbitrary order.SOLUTION: The semiconductor integrated circuit device includes: a plurality of analog ports (AN0-AN3); an A/D conversion section (118) capable of executing an A/D conversion process of converting an analog signal captured via an analog port to a digital signal for each preset virtual channel; and an A/D conversion control section (125) for controlling the operation of the A/D conversion section. The A/D conversion control section includes virtual channel registers capable of setting correspondence relationships between the virtual channels and the analog ports, and a scan group forming register capable of setting a start position and an end position of a scan group. The A/D conversion control section successively executes A/D conversion processes on a plurality of virtual channels from a virtual channel corresponding to a start pointer to a virtual channel corresponding to an end pointer. | ||||||
| 282 | Analog - digital converter and methods, as well as eeg monitoring system, | JP2012507610 | 2009-04-30 | JP5279948B2 | 2013-09-04 | クヌドセン・ニールス・オーレ; キルスゴォア・セレン |
| 283 | Hearing aids and methods with a voice codec | JP2012533481 | 2009-10-15 | JP2013507661A | 2013-03-04 | ランク・マイク・リンド; キドモーセ・プレベン; オングストルプ・ミシャエル; イェンセン・モアテン・ホルム |
| A hearing aid comprising a time domain codec. The codec comprises a decoder adapted to generate a decoded output signal based on an input quantization index and an encoder for generating an output quantization index based on an input signal, said encoder comprising said decoder and a predictor receiving an excitation signal derived from said decoder output signal and outputting a prediction signal. The output quantization index is determined by repeated decoding of the quantization indices in order to minimize the error between the input signal and the prediction signal, and the predictor uses a recursive autocorrelation estimate for the error minimization. The invention further provides a method of encoding an audio signal. | ||||||
| 284 | Solid state imaging device | JP2011161079 | 2011-07-22 | JP2013026904A | 2013-02-04 | OKURA SHUNSUKE; MAKANE MITSUO |
| PROBLEM TO BE SOLVED: To provide a solid state imaging device which reduces instantaneous current generated when transferring image digital signals from analog-digital converters to registers, thereby being capable of reducing wraparound noise to the analog-digital converters or a pixel array.SOLUTION: The solid state imaging device comprises a pixel array 11, a vertical scan circuit 14, plural column ADCs 12, plural registers 17, and control signal generators. The control signal generators are provided at respective groups obtained by dividing the plural column ADCs 12 and the plural registers 17 arranged along one side of the pixel array 11 and generate control signals so as to shift the timing of transferring converted image digital signals from the column ADCs 12 to the registers 17 operating in parallel to each other with respect to each unit including at least one group. | ||||||
| 285 | Analog-to-digital converter and a semiconductor integrated circuit device | JP2011500395 | 2009-02-19 | JP5095007B2 | 2012-12-12 | 俊 大島; 大造 山脇; 友美 高橋 |
| 286 | Eeg input transducer for the monitoring system, signal conversion method and monitoring system | JP2012507610 | 2009-04-30 | JP2012525100A | 2012-10-18 | キルスゴォア・セレン; クヌドセン・ニールス・オーレ |
| モニタされるべき人物によって連続して持ち運ばれることができるＥＥＧモニタリング・システム(40)における雑音および電流消費を最小化するために，ＥＥＧモニタリング・システム用の入力変換器(44)が案出される。 上記入力変換器のアナログ−ディジタル変換器は，入力段，出力段およびフィードバック・ループを備え，上記入力段は増幅器（Ｑ Ａ ）および積分器（RLF）を備える。 変圧器（IT）が上記入力変換中の上記入力段の上流に配置される。 上記変圧器(IT)の変換比はその入力電圧よりも大きな出力電圧を供給する変換比を持ち，これにより，上記入力段についての信号電圧に固定係数が乗算される。 上記変圧器(IT)は少なくとも２つのキャパシタ（Ｃｘ，Ｃｙ，Ｃｚ）を有するスイッチング・キャパシタ変圧器である。 この発明はさらにアナログ信号を変換する方法，および上記入力変換器(44)を備えるＥＥＧモニタリング・システムを提供する。 | ||||||
| 287 | アナログデジタル変換器および半導体集積回路装置 | JP2011500395 | 2009-02-19 | JPWO2010095232A1 | 2012-08-16 | 俊 大島; 山脇 大造; 大造 山脇; 友美 高橋 |
| 従来のタイムインターリーブ型アナログデジタル変換器のデジタルキャリブレーション手法では、次世代アプリケーションの高速サンプルレートに対応し、かつ、高い分解能を実現する高精度なキャリブレーションを行うことができない。これを解決するため、キャリブレーション対象となるタイムインターリーブ型アナログデジタル変換器と共通の入力に、参照用アナログデジタル変換ユニットを並列に接続し、参照用アナログデジタル変換ユニットが出力する低速、高分解能のアナログデジタル変換結果を利用して、タイムインターリーブ型アナログデジタル変換器を構成する各単位アナログデジタル変換ユニットの出力を、デジタル領域でキャリブレーションする。また、上記の参照用アナログデジタル変換ユニットの動作クロック周波数をfCLK/N(ただし、fCLKは、タイムインターリーブ型アナログデジタル変換器全体としてのサンプルレート。また、Nは、単位アナログデジタル変換ユニットの並列数Mと互いに素であること。)とする。この構成によれば、全ての単位アナログデジタル変換ユニットのサンプリングを、参照用アナログデジタル変換ユニットのサンプリングと順次同期させることができ、かつ、参照用アナログデジタル変換器の動作クロック周波数を、タイムインターリーブ型アナログデジタル変換器全体としてのサンプルレートよりN倍低速にできる。 | ||||||
| 288 | Conversion circuit, analog-digital converter, and a method for generating a digital signal corresponding to an analog signal | JP2008520635 | 2007-06-08 | JP4817399B2 | 2011-11-16 | 祥二 川人 |
| 289 | A/d converter and a/d conversion method | JP2010049278 | 2010-03-05 | JP2011188097A | 2011-09-22 | ISHIKAWA KIYOSHI |
| <P>PROBLEM TO BE SOLVED: To obtain an A-D converter and an A-D conversion method of high precision. <P>SOLUTION: The A-D converter includes a reference capacitor group C0 to C5, Cd in which terminal sides of one side are connected to a common signal line SL1, other terminals are connected to a plurality of different reference potential sources VRH, VRL so as to be switchable, and are weighted by predetermined ratios, a capacitive type DAC 11 which includes the reference capacitor group and holds a voltage of an analog input signal, a comparator 12, a sequential conversion control circuit 13 which sequentially switches SW0 to SW5, SWd so that the potential of the common signal line SL1 approaches reference potential based on the comparison result, an offset correction circuit 31 which performs correction stepwise so as to make an offset of the comparator small, and a DAC correction circuit 32 which performs correction stepwise so as to make an error of voltage change of the common signal line small. The offset correction circuit and the DAC correction circuit perform correction so that a residual offset and a residual error of the capacitive type DAC cancel each other. <P>COPYRIGHT: (C)2011,JPO&INPIT | ||||||
| 290 | Gain control with digital processing circuit | JP35151596 | 1996-12-27 | JP4388606B2 | 2009-12-24 | デルマ クリスチャン |
| 291 | Decoding device and method, and recording medium | JP35410698 | 1998-12-14 | JP4189708B2 | 2008-12-03 | 俊之 宮内; 保 池田 |
| 292 | Decoder, method therefor and served medium | JP35410698 | 1998-12-14 | JP2000183756A | 2000-06-30 | IKEDA TAMOTSU; MIYAUCHI TOSHIYUKI |
| PROBLEM TO BE SOLVED: To suppress deterioration in an error characteristic at a change point of a transmission system. SOLUTION: An adder 81A calculates a state metric SM value in the case of transition from a state 00 into a state 01 and outputs the value to a comparator 83A. An adder 82A calculates a state metric SM value in the case of transition from a state 01 into a state 00 and outputs the value to the comparator 83A. The comparator 83A compares the SM values, select a path with a higher likelihood and outputs the result to a set/reset register 84A. An Add Compare Select ACS controller 85 detects that a state transition of fixed information TAB1 is uniquely decided, outputs a reset signal to the set/reset register 84A that stored the SM value denoting the state to set 0 to its register contents, and outputs a set signal to set/reset registers 84B-84D that store SM values denoting other state than the state 00 of the fixed information TAB 1 to set a MAX value to the contents of the registers. | ||||||
| 293 | JPS6358501B2 - | JP13257282 | 1982-07-29 | JPS6358501B2 | 1988-11-16 | |
| PURPOSE:To perform switching to remote maintenance while holding a normal operation state, by grasping the state of a data processor through a communication circuit and transferring data corresponding to the state between the data processor and a maintenance center device. CONSTITUTION:Data is transferred in series between the logical circuit 9 of the data processor and a console panel 7 or maintenance center device. Then, the data processor is provided with a switching circuit for switching between the key information of the console panel 7 and remote maintenance data, and the output of the switching circuit is sent to a receiving shift register 21. The contents of this register 21 are stored in a storage register 22 and outputted to the circuit 9. Then, the circuit 9 outputs display information through a display information transfer register 23. Consequently, the switching circuit is used to output the key information and display information to a remote maintenance interface. | ||||||
| 294 | Digital/analog converter | JP7887887 | 1987-03-31 | JPS63245129A | 1988-10-12 | HASHIMOTO YOICHI; TOKUYAMA TAKASHI; NISHIMUKAI KAZUYA; ARAI YOSHIHIRO; UEKI NOBUHIDE; ADACHI NAOKI |
| PURPOSE: To reproduce an original signal with fidelity without phase distortion by generating sequentially a unit pulse response signal at every prescribed time and generating a digital data DT at every prescribed time and multiplying a prescribed digital value with the unit pulse response signal so as to apply digital/analog conversion. CONSTITUTION: A unit pulse response signal generator 12 generates a unit pulse response signal SP of a partial waveform S k at every sampling time ΔT and gives the result to a multiplication section 13. The multiplication section 13 has n-set of multiplication type D/A converters (multiplication circuit) 13 -4∼13 4, the multiplication circuit 13 -4 multiplies a digital data stored in a latch circuit 11c -4 with a partial waveform S -4 to output an analog signal M -4, and the multiplication circuit 13 -3 multiplies the digital data stored in the latch circuit 11c -3 with the partial waveform S -3 to output an analog signal M -3, and similarly each multiplication circuit 13 k multiplies the digital data stored in the latch circuit 11c k with the partial waveform S k to output an analog signal M k. COPYRIGHT: (C)1988,JPO&Japio | ||||||
| 295 | JPS6025743B2 - | JP16060877 | 1977-12-28 | JPS6025743B2 | 1985-06-20 | OKADA TAKAFUMI |
| 296 | JPS5953506B2 - | JP7031278 | 1978-06-13 | JPS5953506B2 | 1984-12-25 | TAKASE SADAO |
| 297 | Reference-voltage supplying circuit | JP792681 | 1981-01-23 | JPS57123729A | 1982-08-02 | YAMAKIDO KAZUO; KIKUCHI HIROYUKI |
| PURPOSE:To eliminate the need for a control terminal by selecting a reference voltage on the basis of the level of the reference voltage supplied from an external terminal. CONSTITUTION:An external reference voltage VEXT supplied to an external reference voltage input terminal 1 is discriminated on the basis of an input threshold voltage value VTH determined by an inverter circuit 21 to output lines 3 and 4 binary signals which have mutually complementary logical levels and switch analog switches 6 and 7 complementarily. When the external reference voltage vEXT is lower than the threshold voltage value VTH, a voltage having a value VINT is applied from an internal reference voltage source 5 to an output terminal 8. When not, the analog switch 6 is closed, so the external reference voltage source 5 to an output terminal 8. When not, the analog switch 6 is closed, so the external reference voltage is developed at the output terminal 8. | ||||||
| 298 | R-2r resistor circuit network | JP18851981 | 1981-11-26 | JPS57116420A | 1982-07-20 | HORUGAA SHIYUTORUTOFU |
| 299 | JPS5733726B1 - | JP8745070 | 1970-10-06 | JPS5733726B1 | 1982-07-19 | |
| 300 | JPS559008Y2 - | JP1431578 | 1978-02-07 | JPS559008Y2 | 1980-02-27 | |
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