| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | Duo-binary encoder and optical duo-binary transmission apparatus using the same | JP2004348241 | 2004-12-01 | JP2005168023A | 2005-06-23 | KIM SUNG-KEE; LEE HAN-LIM; HWANG SEONG-TEAK |
| PROBLEM TO BE SOLVED: To provide a duo-binary encoder and an optical duo-binary transmission apparatus in which acceleration can be performed while using an existing low-speed electrical element. SOLUTION: The optical duo-binary encoder includes: a level change detection unit 410 for detecting that levels of data input signals of N channels inputted at an n-th input of channels change from 0 to 1, or from 1 to 0; a determination unit 420 for judging whether the number of level changes detected by the level change detection unit is odd or even; a toggle unit 430 for toggling an output signal of the determination unit when the number of level changes is odd; an intermediate signal generation unit 440 for determining whether phases of other channels are shifted or not according to a data input signal on the basis of a predetermined channel of the N channels; and a phase division unit 450 for dividing data into a data group having non-shifted phases and another data group which requires a phase shift according to an output signal of the intermediate signal generation unit and the data input signal, and outputting the divided data groups. COPYRIGHT: (C)2005,JPO&NCIPI | ||||||
| 22 | Input output interface and semiconductor integrated circuit | JP2001219519 | 2001-07-19 | JP2003032084A | 2003-01-31 | MATSUZAKI YASURO; SHINOZAKI NAOHARU |
| PROBLEM TO BE SOLVED: To reduce power consumption by transmitting a huge amount data with a few number of signal lines in an input output interface that transmits/ receives a signal. SOLUTION: The input output interface expresses logical values according to the sequence of timings of transition edges of a plurality of signals respectively transmitted through a plurality of signal lines or expresses logical values according to a time difference between the transition edges of signals transmitted through the signal lines and a transition edges of a reference timing signal. Thus, one signal line can transmits a huge amount of data. Since huge amount of data can be transmitted by one signal transmission, the transfer rate of data can considerably be enhanced. Since a small number of signal lines is enough for the transmission, number of signal input circuits and signal output circuits can be reduced to decrease the power consumption. Further, since a small number of the signal lines is enough for the transmission, the wiring region of the signal lines can be decreased. COPYRIGHT: (C)2003,JPO | ||||||
| 23 | Device and method for modulation and demodulation | JP15373799 | 1999-06-01 | JP2000349843A | 2000-12-15 | TAKAYAMA YOSHINUSHI |
| PROBLEM TO BE SOLVED: To accelerate data transmission without inviting an increase in costs by providing a demodulating means which performs septenary conversion of data inputted through an antenna after performing octonary demodulation of the data. SOLUTION: A modulator 10 as a modulating means performs septenary conversion of inputted voice or other data and subsequently modulates the voice or the data by using a carrier. An amplifier 11 amplifies an output from the modulator 10 with a prescribed value. A DUP 12 transmits a signal amplified by the amplifier 11 from an antenna 17. Then, an amplifier 13 amplifies a signal fetched through the antenna 17 and the DUP 12 with a prescribed value. An intermediate frequency amplifier 15 amplifies the intermediate frequency of the signal amplified by the amplifier 13. A demodulator 16 as a demodulating means also demodulates and outputs the intermediate frequency amplified by the amplifier 15. Then, the demodulator 16 performs octonary demodulation of the inputted voice or the other data and subsequently performs septenary conversion. COPYRIGHT: (C)2000,JPO | ||||||
| 24 | Null rule threshold gate | JP52083096 | 1996-01-05 | JPH10511825A | 1998-11-10 | ジェラルド・イー ソーベルマン、; カール・エム ファント、 |
| (57)【要約】 ヌル規則しきい値ゲート（921 ）が、それぞれ断定状態とヌル状態とを持つ複数の入力（Ｘ１，Ｘ２，………Ｘｎ）を受け入れる。 しきい値ゲートは、断定入力の数がしきい値数を越えた時に、その出力（Ｚ）を断定状態に切り替える。 しきい値ゲートは、すべての入力がヌルに戻った後のみ、その出力をヌル状態に切り替える。 信号状態は異なる電流レベルとして実現される。 | ||||||
| 25 | Systems and methods for efficient soft data based flash memory data recovery | US14925714 | 2015-10-28 | US10108489B2 | 2018-10-23 | Zhijun Zhao; Shaohua Yang; Victor Krachkovsky |
| Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory. | ||||||
| 26 | METHOD AND DEVICE FOR GENERATING A DECODED AND SYNCHRONIZED OUTPUT | US15198487 | 2016-06-30 | US20180006668A1 | 2018-01-04 | Marco Jan-Jaco WIELAND |
| The invention relates to a invention relates to a method and decoding device for receiving an input bit-stream comprising a sequence of n-bit pattern symbols as well as a unique n-bit comma symbol for synchronization, and for generating therefrom a synchronized output comprising a sequence of m-bit pattern words, with m | ||||||
| 27 | Systems and Methods for Efficient Soft Data Based Flash Memory Data Recovery | US14925714 | 2015-10-28 | US20170123899A1 | 2017-05-04 | Zhijun Zhao; Shaohua Yang; Victor Krachkovsky |
| Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory. | ||||||
| 28 | Low complexity non-integer adaptive sample rate conversion | US14336132 | 2014-07-21 | US09264065B2 | 2016-02-16 | Gregary B. Prince |
| Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency. The sample rate converter can include a multiplier configured to produce an output that is the product of a filter coefficient of the filter coefficients from the numerically controlled oscillator and a sample of an input signal and an accumulator configured to sum an output of the multiplier and provide a result of the summation when the accumulator receives an indicator to dump the result. | ||||||
| 29 | Bus signal encoded with data and clock signals | US13739749 | 2013-01-11 | US09041564B2 | 2015-05-26 | Perry H. Pelley |
| A CODEC includes a transmission path between an encoder and a decoder. The encoder receives bits of data in a first form in which each bit of the data is represented by switching between first and second logic states and no voltage change between consecutive bits of the same logic state and serially transmits the bits in a second form in which the first logic state is maintained at a high voltage, the second logic state is maintained at a low voltage, and an intermediate voltage is maintained between consecutive bits. The decoder receives the bits in the second form and derives a clock from the occurrences of the intermediate voltage. The clock, repetitively, is maintained at a logic high, then switches directly from the logic high to a logic low, then is maintained at the logic low, and then switches directly between the logic low and the logic high. | ||||||
| 30 | DYNAMIC DECODING OF COMMUNICATION BETWEEN CARD READER AND PORTABLE DEVICE | US14458389 | 2014-08-13 | US20150051914A1 | 2015-02-19 | Fredrik ANDERSSON |
| The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises pre-processing the received encoded data signal; scanning the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating an actual frequency based on the detected start sequence; interpreting, a data block succeeding the start sequence using the assessed actual frequency; and assessing whether to request adjustment of the adjustable encoder clock frequency based on the scanning and/or the interpretation. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program. | ||||||
| 31 | METHODS AND APPARATUSES FOR LOW-POWER MULTI-LEVEL ENCODED SIGNALS | US14506902 | 2014-10-06 | US20150022383A1 | 2015-01-22 | TIMOTHY M. HOLLIS |
| Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data. | ||||||
| 32 | Methods and apparatuses for low-power multi-level encoded signals | US13475728 | 2012-05-18 | US08854236B2 | 2014-10-07 | Timothy M. Hollis |
| Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data. | ||||||
| 33 | BUS SIGNAL ENCODED WITH DATA AND CLOCK SIGNALS | US13739749 | 2013-01-11 | US20140197976A1 | 2014-07-17 | PERRY H. PELLEY |
| A CODEC includes a transmission path between an encoder and a decoder. The encoder receives bits of data in a first form in which each bit of the data is represented by switching between first and second logic states and no voltage change between consecutive bits of the same logic state and serially transmits the bits in a second form in which the first logic state is maintained at a high voltage, the second logic state is maintained at a low voltage, and an intermediate voltage is maintained between consecutive bits. The decoder receives the bits in the second form and derives a clock from the occurrences of the intermediate voltage. The clock, repetitively, is maintained at a logic high, then switches directly from the logic high to a logic low, then is maintained at the logic low, and then switches directly between the logic low and the logic high. | ||||||
| 34 | METHODS AND APPARATUSES FOR LOW-POWER MULTI-LEVEL ENCODED SIGNALS | US13475728 | 2012-05-18 | US20130307708A1 | 2013-11-21 | Timothy M. Hollis |
| Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data. | ||||||
| 35 | ENCODING METHOD, ENCODING APPARATUS, DECODING METHOD, DECODING APPARATUS, AND SYSTEM | US13722206 | 2012-12-20 | US20130181851A1 | 2013-07-18 | Masahiro Kataoka |
| An encoding method includes searching a search target symbol string within a specific range from the end of a symbol string, which has been utilized for encoding, for a match symbol string corresponding to a beginning symbol string of a symbol string to be encoded, encoding the beginning symbol string based on a distance between the match symbol string and the beginning symbol string, and a length of the match symbol string. | ||||||
| 36 | Decoding Method for Biphase-Encoded Data | US13239699 | 2011-09-22 | US20130076543A1 | 2013-03-28 | Xian-Feng Yang; Xiao-Qin Guo |
| A decoding method for biphase-encoded data is provided. The decoding method includes detecting falling-edge transitions in the biphase-encoded data to decode according to a time difference (Δt) between each two adjacent falling-edge transitions and the logic value of previous bit. When Δt is 1 bit period and previous bit is logic 1, it's determined that present bit is logic 1. When Δt is 1 bit period and previous bit is logic 0, it's determined that present bit is logic 0. When Δt is 1.5 bit periods and previous bit is logic 1, it's determined that present and next bits are both logic 0. When Δt is 1.5 bit periods and previous bit is logic 0, it's determined that present bit is logic 1. When Δt is 2 bit periods and previous bit is logic 1, it's determined that present and next bits are logic 0 and 1 respectively. | ||||||
| 37 | Systems and Methods for Variable Rate Conversion | US13552523 | 2012-07-18 | US20130038475A1 | 2013-02-14 | Ragnar H. Jonsson; Vilhjalmur S. Thorvaldsson; Trausti Thormundsson |
| Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter. | ||||||
| 38 | Systems and methods for variable rate conversion | US12488322 | 2009-06-19 | US07920078B2 | 2011-04-05 | Ragnar H Jonsson; Vilhjalmur S Thorvaldsson; Trausti Thormundsson |
| Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter. | ||||||
| 39 | Hardware efficient implementation of finite impulse response filters with limited range input signals | US11748923 | 2007-05-15 | US07411523B2 | 2008-08-12 | Christian Lutkemeyer |
| Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two. This in turn may reduce the number of adders in each tap multiplier of the FIR filter from two to one, resulting in lower area, lower power dissipation, and potentially higher switching speeds. | ||||||
| 40 | MB810 encoder/decoder, dual mode encoder/decoder, and MB810 code generating method | US10848944 | 2004-05-19 | US07290202B2 | 2007-10-30 | Sungsoo Kang; Tae Whan Yoo; Hyeong Ho Lee |
| An MB810 encoder and/or decoder, dual mode encoder and/or decoder, and a method for generating MB810 codes are provided. Twelve state points in the form of a 4×3 matrix on a state transition map are formed with binary unit digital sum variation & alternate sum variation (BUDA). A 10-bit code from 8-bit data is generated outputting a 10-bit code from a predetermined state point to form the matrix. Codes forming a complementary pair from a set of codes capable of arriving at state points forming the matrix are selected. Codes forming the 12 state points by supplementing state points lacked in the codes forming a complementary pair are selected. Control codes including IDLE code from the codes forming the 12 state points are selected. Codes generating the IDLE code by a bit string between neighboring codes among the codes forming the 12 state points are removed. | ||||||
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