| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | ENCODER RESOLUTION REDUCTION | EP13872262.4 | 2013-01-18 | EP2946476A1 | 2015-11-25 | KANG, Keunmo; CULP, Slade, R.; BOGLI, Craig, Drew; VERONESI, William, A.; MARVIN, Daryl, J. |
| One or more embodiments are directed to an encoder configured to output a signal, and a computing device configured to receive the signal from the encoder and generate a reduced resolution version of the signal, the computing device is configured to transmit the reduced resolution version of the signal to a recipient. | ||||||
| 102 | Dynamic decoding of communication between card reader and portable device | EP13195098.2 | 2013-11-29 | EP2838203A2 | 2015-02-18 | Andersson, Fredrik |
The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises preprocessing S1 the received encoded data signal; scanning S2 the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating S3 an actual frequency based on the detected start sequence; interpreting S4, a data block succeeding the start sequence using the assessed actual frequency; and assessing S5 whether to request adjustment S5 of the adjustable encoder clock frequency based on the scanning S2 and/or the interpretation S4. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program.
|
||||||
| 103 | Data decoding apparatus and data decoding method | EP00304380.9 | 2000-05-24 | EP1056084B1 | 2004-01-28 | Yoshinaka, Tadaaki, c/o Sony Corporation |
| 104 | Input/output interface and semiconductor integrated circuit having input/output interface | EP01310174.6 | 2001-12-05 | EP1286470A2 | 2003-02-26 | Matsuzaki, Yasurou, c/o Fujitsu Limited |
An input/output interface is provided in which a logical value is expressed by an order that transition edges appear in a plurality of transmission signals transmitting respectively on a plurality of signal lines (DA, DB, DC, DD). Otherwise, the logical value is expressed by a time difference between the transition edge of the transmission signal transmitting on the signal line and a transition edge of a standard timing signal. Therefore, a large amount of data can be transmitted through one signal line. Since a large amount of data can be transmitted by one transmission, it is possible to substantially increase the data transfer rate. Since only a small number of the signal lines are necessary, it is possible to reduce the number of input circuits and output circuits of the transmission signals, to reduce power consumption, and to reduce the wiring area of the signal lines. |
||||||
| 105 | Data decoding apparatus and data decoding method | EP00304380.9 | 2000-05-24 | EP1056084A2 | 2000-11-29 | Yoshinaka, Tadaaki, c/o Sony Corporation |
This invention relates to a data decoding apparatus and data decoding method which perform maximum likelihood decoding by means of a simple construction, and which can be applied for example to a videotape recorder or optical disk device. In the data decoding apparatus or data decoding method a logic level inversion timing during one clock interval is detected from an input signal, a provisional identification result (22) of identifying the input signal is corrected by effectively one clock identification error, the number of state transitions which can be obtained from the input signal is limited based on this corrected provisional identification result, and the most probable state transition of these limited state transitions is detected to output an input signal identification result. |
||||||
| 106 | Vector signaling with reduced receiver complexity | US15635012 | 2017-06-27 | US09985745B2 | 2018-05-29 | Amin Shokrollahi |
| Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power. | ||||||
| 107 | METHOD FOR ENCODING REAL NUMBER M-ARY SIGNAL AND ENCODING APPARATUS USING SAME | US15561904 | 2015-04-21 | US20180123839A1 | 2018-05-03 | Hae Chung; Han Chung |
| Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N1 number of M1-ary signals, a second signal generator which receives the second input code and generates N2 number of M2-ary signals, and a first time division multiplexing module which temporally multiplexes the N1 number of M1-ary signals and the N2 number of M2-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A2/A1) used for M1-ary and M2-ary signals to minimize a transmission error rate. | ||||||
| 108 | RECEIVER, SENDER, METHOD FOR RETRIEVING AN ADDITIONAL DATUM FROM A SIGNAL AND METHOD FOR TRANSMITTING A DATUM AND AN ADDITIONAL DATUM IN A SIGNAL | US15840574 | 2017-12-13 | US20180102786A1 | 2018-04-12 | Dirk Hammerschmidt |
| A receiver includes a receiver circuit to receive a first transition in a first direction, a second transition in a second, different direction after the first transition and a third transition in the first transition after the second transition of a signal. A first time period between the first and third transitions is indicative of a datum to be received. The receiver circuit is also configured to determine a second time period between the first transition and a second transition and to determine an additional datum to be received based at least on the determined second time period between the first and second transitions. Using the determined second time period allows for more information to be received in a reliable manner. | ||||||
| 109 | Method and device for generating a decoded and synchronized output | US15198487 | 2016-06-30 | US09887707B2 | 2018-02-06 | Marco Jan-Jaco Wieland |
| The invention relates to a invention relates to a method and decoding device for receiving an input bit-stream comprising a sequence of n-bit pattern symbols as well as a unique n-bit comma symbol for synchronization, and for generating therefrom a synchronized output comprising a sequence of m-bit pattern words, with m | ||||||
| 110 | Method and apparatus for compressing LUT | US15098904 | 2016-04-14 | US09864699B1 | 2018-01-09 | Wei Xu; Fei Sun; Ka-Ming Keung; Jinjin He; Young-Ta Wu; Tony Yoon |
| Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT. | ||||||
| 111 | DIGITAL TIME CONVERTER SYSTEMS AND METHODS | US15583063 | 2017-05-01 | US20180006658A1 | 2018-01-04 | Georgios Yorgos Palaskas; Paolo Madoglio; Peter Preyler; Rotem Banin |
| A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal. | ||||||
| 112 | Dynamic decoding of communication between card reader and portable device | US14458389 | 2014-08-13 | US09805730B2 | 2017-10-31 | Fredrik Munter |
| The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises pre-processing the received encoded data signal; scanning the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating an actual frequency based on the detected start sequence; interpreting, a data block succeeding the start sequence using the assessed actual frequency; and assessing whether to request adjustment of the adjustable encoder clock frequency based on the scanning and/or the interpretation. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program. | ||||||
| 113 | Configuring signal-processing systems | US14712539 | 2015-05-14 | US09472304B2 | 2016-10-18 | Jesper Steensgaard-Madsen; Manideep Gande |
| A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal. | ||||||
| 114 | Mechanism for data generation in data processing systems | US14718407 | 2015-05-21 | US09437277B1 | 2016-09-06 | James A. Welker; Joshua Siegel |
| An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data. | ||||||
| 115 | METHODS AND APPARATUS TO REDUCE SIGNALING POWER | US14855115 | 2015-09-15 | US20160006587A1 | 2016-01-07 | Timothy Mowry Hollis |
| System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. | ||||||
| 116 | ENCODER RESOLUTION REDUCTION | US14760897 | 2013-01-18 | US20150365103A1 | 2015-12-17 | Keunmo Kang; Slade Culp; Craig Drew Bogli; William A. Veronesi; Daryl J. Marvin |
| One or more embodiments are directed to an encoder configured to output a signal, and a computing device configured to receive the signal from the encoder and generate a reduced resolution version of the signal, the computing device is configured to transmit the reduced resolution version of the signal to a recipient. | ||||||
| 117 | Methods and apparatus to reduce signaling power | US14089683 | 2013-11-25 | US09172567B2 | 2015-10-27 | Timothy Mowry Hollis |
| System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. | ||||||
| 118 | Methods and apparatuses for low-power multi-level encoded signals | US14506902 | 2014-10-06 | US09148170B2 | 2015-09-29 | Timothy M. Hollis |
| Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data. | ||||||
| 119 | METHOD AND APPARATUS FOR VALID ENCODING | US14608319 | 2015-01-29 | US20150212156A1 | 2015-07-30 | Ido BOURSTEIN |
| Aspects of the disclosure provide a circuit including an encoding circuit and a valid circuit. The encoding circuit is configured to encode data to be transmitted as signals on a data bus to satisfy a requirement that limits a number of bit transitions between consecutive transmissions. The valid circuit is configured to selectively corrupt the signals not to satisfy the requirement that limits the number of bit transitions between the consecutive transmissions to indicate whether the signals to be transmitted on the data bus constitute valid data or invalid data. | ||||||
| 120 | METHODS AND APPARATUS TO REDUCE SIGNALING POWER | US14089683 | 2013-11-25 | US20150146816A1 | 2015-05-28 | Timothy Mowry Hollis |
| System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. | ||||||
QQ群二维码
意见反馈
意见反馈