序号 专利名 申请号 申请日 公开(公告)号 公开(公告)日 发明人
81 Doubletpulse generator US790313 1991-11-08 US5198700A 1993-03-30 Frank A. Whiteside
An interface for current mode to Manchester encoded serial signals includes symmetric positive/negative doublet pulse generation. The doublet pulse generator provides a pulse duration held constant by feedback and a voltage/current reference and a minimal gap between the positive and negative polarity pulses by using the same signal to both turn off the positive pulse driver and turn on the negative pulse driver. Fault detection by sensing of asymmetry in received pulse uses a comparator with both high and low threshold input devices to provide minor asymmetry tolerance.
82 METHOD AND SYSTEM FOR BI-PHASE MARK CODING (BMC) DECODING EP17203164.3 2017-11-22 EP3334051A3 2018-09-26 Smith, Ronald Dean; Zhang, Xu; Svoiski, Mikhail; Ferguson, Jason Ryan

Embodiments of methods and systems for BMC decoding are described. In an embodiment, a method for BMC decoding involves performing a unit interval estimation of a BMC encoded bit stream, locating a bit boundary of the BMC encoded bit stream based on the unit interval estimation and a known sequence in a preamble of the BMC encoded bit stream, and measuring a time duration across multiple bit transitions from the bit boundary and decoding the BMC encoded bit stream based on the time duration and the unit interval estimation.

83 VECTOR SIGNALING WITH REDUCED RECEIVER COMPLEXITY EP14818292 2014-06-24 EP2997704A4 2017-03-15 SHOKROLLAHI AMIN
Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.
84 MECHANISM FOR DATA GENERATION IN DATA PROCESSING SYSTEMS EP16170416.8 2016-05-19 EP3096232A1 2016-11-23 Siegel, Joshua; Welker, James

An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.

85 METHODS AND APPARATUSES FOR LOW-POWER MULTI-LEVEL ENCODED SIGNALS EP13791081 2013-05-17 EP2850616A4 2016-04-06 HOLLIS TIMOTHY M
Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.
86 Dynamic decoding of communication between card reader and portable device EP13195098.2 2013-11-29 EP2838203A3 2015-06-03 Andersson, Fredrik

The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises preprocessing S1 the received encoded data signal; scanning S2 the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating S3 an actual frequency based on the detected start sequence; interpreting S4, a data block succeeding the start sequence using the assessed actual frequency; and assessing S5 whether to request adjustment S5 of the adjustable encoder clock frequency based on the scanning S2 and/or the interpretation S4. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program.

87 A MOVEABLE BARRIER OPERATOR TRANSLATION SYSTEM AND METHOD EP08878329.5 2008-11-19 EP2425328A1 2012-03-07 FITZGIBBON, James, J.; MACK, David, Thomas; KELLER, Robert, Jr.; STRAIT, Larry
A system includes a translator device that is configured to receive, using a pre-programmed native mode of operation, a first barrier actuation code transmitted by a transmitter according to a first code format. The translator device then analyzes the first barrier actuation code and verifies that it is a valid code. When a valid code, the translator device saves the information contained in the code, and creates a second barrier actuation code at least in part from information contained in the first actuation code and transmits the second barrier actuation code according to the second code format, which is different from the first code format. A barrier operator is coupled to the translator device and a barrier. The barrier operator has a receiver apparatus and the receiver apparatus receives the second barrier actuation code. The barrier operator determines whether the second barrier actuation code is valid, and when the barrier actuation code is determined to be valid, actuates the barrier.
88 Input/output interface and semiconductor integrated circuit having input/output interface EP01310174.6 2001-12-05 EP1286470B1 2011-11-02 Matsuzaki, Yasurou, c/o Fujitsu Limited
89 Input/output interface and semiconductor integrated circuit having input/output interface EP06010162.3 2001-12-05 EP1701447A2 2006-09-13 Matsuzaki, Yasurou c/o Fujitsu Limited

An input/output interface is provided in which a logical value is expressed by a time difference between the transition edge of the transmission signal transmitting on the signal line (DATA) and a transition edge of a standard timing signal (CLK). Therefore, a large amount of data can be transmitted through one signal line. Since a large amount of data can be transmitted by one transmission, it is possible to substantially increase the data transfer rate. Since only a small number of the signal lines are necessary, it is possible to reduce the number of input circuits and output circuits of the transmission signals, to reduce power consumption, and to reduce the wiring area of the signal lines.

90 Modem voice/data mode switching arrangement. EP99108715.6 1999-04-30 EP0953966A2 1999-11-03 Shinta, Minoru, c/o NEC Miyagi, Ltd.

A voice signal or a modem signal input into a transmitter is coded, and the coded signal is transmitted from the transmitter to a receiver through a digital transmission line. In this voice coding apparatus, when the input modem signal is a modem signal output from a high-speed modem, it is transmitted without low bit rate compression. By virtue of this constitution, the voice coding apparatus can realize high-speed modem transmission not involving a lowering in transmission speed.

91 NULL CONVENTION SPEED INDEPENDENT LOGIC EP92913146 1992-05-15 EP0584265A4 1994-05-18 FANT KARL M; BRANDT SCOTT A
An information processing system comprising at least one information processing unit (A, B). The information processing unit has at least one information processing member which resolves allowed values. Allowed values include at least one data value and at least one non-data value. At least one non-data value is a null value. The system further comprises a plurality of information transmission elements (OA, NA) for transmitting values to and from the information processing unit (A) and the information processing member.
92 NULL CONVENTION SPEED INDEPENDENT LOGIC EP92913146.0 1992-05-15 EP0584265A1 1994-03-02 FANT, Karl, M.; BRANDT, Scott A.
Système de traitement d'informations comprenant au moins une unité de traitement d'informations (A, B). L'unité de traitement d'informations comporte au moins un élément de traitement d'informations qui traduit des valeurs admises. Lesdites valeurs admises comprennent au moins une valeur auxiliaire. Au moins une valeur auxiliaire est une valeur nulle. Le système comprend en outre une pluralité d'éléments de transmission d'informations (OA; NA) qui transmettent des valeurs en provenance et en direction de l'unité de traitement d'informations (A) et de l'élément de traitement d'informations.
93 DEVICE AND METHODS FOR BIPHASIS PULSE SIGNAL CODING PCT/US2006030886 2006-08-08 WO2007019498A2 2007-02-15 CHEN DU; HARRIS JOHN G; PRINCIPE JOSE C
A method for coding time signals based on generating an asynchronous biphasic pulse train is provided. The method includes generating response signals based upon one or more input signals. A pulse comprises a positive pulse if a voltage of the response signal is greater than a predetermined positive voltage threshold. A pulse comprises a negative pulse if the voltage of the response signal is less than a predetermined negative voltage threshold. The method further includes a method for the reconstruction of a uniformly sampled version of the original signal.
94 MECHANISM FOR DATA GENERATION IN DATA PROCESSING SYSTEMS EP16170416.8 2016-05-19 EP3096232B1 2018-10-17 Siegel, Joshua; Welker, James
An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.
95 METHOD AND SYSTEM FOR BI-PHASE MARK CODING (BMC) DECODING EP17203164.3 2017-11-22 EP3334051A2 2018-06-13 Smith, Ronald Dean; Zhang, Xu; Svoiski, Mikhail; Ferguson, Jason Ryan

Embodiments of methods and systems for BMC decoding are described. In an embodiment, a method for BMC decoding involves performing a unit interval estimation of a BMC encoded bit stream, locating a bit boundary of the BMC encoded bit stream based on the unit interval estimation and a known sequence in a preamble of the BMC encoded bit stream, and measuring a time duration across multiple bit transitions from the bit boundary and decoding the BMC encoded bit stream based on the time duration and the unit interval estimation.

96 METHOD FOR ENCODING REAL NUMBER M-ARY SIGNAL AND ENCODING APPARATUS USING SAME EP15887841.3 2015-04-21 EP3276835A1 2018-01-31 CHUNG, Hae; CHUNG, Han

Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N1 number of M1-ary signals, a second signal generator which receives the second input code and generates N2 number of M2-ary signals, and a first time division multiplexing module which temporally multiplexes the N1 number of M1-ary signals and the N2 number of M2-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A2/A1) used for M1-ary and M2-ary signals to minimize a transmission error rate.

97 DIGITAL TIME CONVERTER SYSTEMS AND METHODS EP17174855.1 2017-06-07 EP3264599A1 2018-01-03 PALASKAS, Georgios Yorgos; MADOGLIO, Paolo; PREYLER, Peter; BANIN, Rotem

A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

98 METHODS AND APPARATUS TO REDUCE SIGNALING POWER EP14821340.8 2014-11-21 EP3075117A1 2016-10-05 HOLLIS, Timothy Mowry
System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.
99 VECTOR SIGNALING WITH REDUCED RECEIVER COMPLEXITY EP14818292.6 2014-06-24 EP2997704A1 2016-03-23 SHOKROLLAHI, Amin
Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.
100 DATA COMPRESSION METHOD, AND REDUCTION METHOD, DEVICE AND SYSTEM EP13877388.2 2013-03-07 EP2953303A1 2015-12-09 QIN, Fengping

The present invention relates to a data compression method, a data restoration method, apparatuses, and a system. The data compression method includes: acquiring a first digital signal; acquiring a first compressed signal by performing down-sampling processing on the first digital signal, where a sampling frequency of the first compressed signal is not less than a frequency threshold, and the frequency threshold is twice a baseband cut-off frequency of the first digital signal; and sending the first compressed signal by using a transmission format based on the common public radio interface CPRI protocol. Frequency decrease is performed before data is transmitted by using the CPRI protocol, so as to reduce an amount of data to be transmitted by using a CPRI, and improve data transmission efficiency, or, in other words, increase a quantity of RRUs or BBUs that can be supported on per CPRI.

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