| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | System and method for adjusting a non-return to zero data stream input threshold | US10077274 | 2002-02-15 | US07107499B1 | 2006-09-12 | Omer Fatih Acikel; Warm Shaw Yuan; Daniel M. Castagnozzi |
| A state machine method and system are provided for determining non-causal channel equalization thresholds. The method comprises: receiving a non-return to zero (NRZ) data stream encoded with forward error correction (FEC); setting x=0; in State 0, adjusting a third threshold (Vopt) in response to corrected bit errors; if x=0, setting a first and second threshold equal to the third threshold; in State 1, if x=0, simultaneously adjusting the first threshold and the second threshold, to minimize the total number of corrected bit errors; in State 2, following State 0, adjusting the first threshold, independent of the second threshold, to minimize the total number of errors; in State 3, following State 0, adjusting the second threshold, independent of the first threshold, to minimize the total number of errors; and, adding 1 to x and returning to State 0. | ||||||
| 42 | Dual mode decoder | US11231415 | 2005-09-20 | US20060012496A1 | 2006-01-19 | Sungsoo Kang; Tae Yoo; Hyeong Lee |
| A dual mode decoder is provided. The dual mode decoder includes an MB810 decoder; an 8B/10B decoder; a mode detection unit which detects a decoder to be used as an operation decoder between the MB810 decoder and the 8B/10B decoder; a first low pass filter which when the MB810 decoder is determined as the operation decoder, removes a predetermined frequency bandwidth from a 10-bit code input from the outside; a second low pass filter which when the 8B/10B decoder is determined as the operation decoder, removes a predetermined frequency bandwidth from a 10-bit code input from the outside; an IDLE code detection unit which detects IDLE code from the 10-bit code and transfers to the mode detection unit; a first switch unit which according to the decoder determined as the operation decoder, selectively outputs the 10-bit code input from the first low pass filter and the second low pass filter; a parallel conversion unit which converts the 10-bit code input from the first switch into a parallel code and outputs a 10-bit parallel code; a first selection unit which provides the 10-bit parallel code to the decoder determined as the operation decoder between the MB810 decoder and the 8B/10B decoder; and a second selection unit which selectively outputs an 8-bit code corresponding to the 10-bit parallel code input from the decoder determined as the operation decoder. | ||||||
| 43 | DUO-BINARY ENCODER AND OPTICAL DUO-BINARY TRANSMISSION APPARATUS | US10858919 | 2004-06-02 | US20050116841A1 | 2005-06-02 | Sung-Kee Kim; Han-Lim Lee; Seong-Taek Hwang |
| An optical duo-binary transmission apparatus using an optical duo-binary transmission method is disclosed. The apparatus includes a duo-binary encoder that performs parallel processing. The duo-binary encoder includes a level change detection unit for detecting that levels of data input signals of N channels input at an nth input of channels change from 0 to 1, or from 1 to 0; a judgment unit for judging whether a number of level changes detected by the level change detection unit is odd or even; and a toggle unit for toggling an output signal of the judgment unit when the number of level change is odd. The encoder also includes an intermediate signal generation unit for determining whether phases of other channels are shifted or not, according to an data input signal on the basis of a predetermined channel of the N channels; and a phase division unit for dividing data into a first data group having non-shifted phases and a second data group which require a phase shift, according to an output signal of the intermediate signal generation unit and the data input signal, and outputting the divided first and second data groups. | ||||||
| 44 | Hardware efficient implementation of finite impulse response filters with limited range input signals | US10774151 | 2004-02-05 | US06864812B1 | 2005-03-08 | Christian Lutkemeyer |
| Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a fill duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel. The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two. This in turn may reduce the number of adders in each tap multiplier of the FIR filter from two to one, resulting in lower area, lower power dissipation, and potentially higher switching speeds. | ||||||
| 45 | Data decoding apparatus and data decoding method | US09579732 | 2000-05-26 | US06373413B1 | 2002-04-16 | Tadaaki Yoshinaka |
| This invention relates to a data decoding apparatus and data decoding method which perform maximum likelihood decoding by means of a simple construction, and which can be applied for example to a videotape recorder or optical disk device. In the data decoding apparatus or data decoding method according to this invention, a logic level inversion timing during one clock interval is detected from an input signal, a provisional identification result of identifying the input signal is corrected by effectively one clock identification error, the number of state transitions which can be obtained from the input signal is limited based on this corrected provisional identification result, and the most probable state transition of these limited state transitions is detected to output an input signal identification result. Further, in the data decoding apparatus or data decoding method according to this invention, a provisional identification result is obtained by identifying an input signal by effectively one clock identification error, a logic level inversion interval is corrected when a logic level inversion interval occurs in a shorter interval than a permitted logic level inversion interval in the input signal, the number of state transitions which can be obtained from the input signal is limited based on this corrected provisional identification result, and the most probable state transition of these limited state transitions is detected to output an input signal identification result. | ||||||
| 46 | NULL convention logic system | US220636 | 1994-03-31 | US5664212A | 1997-09-02 | Karl M. Fant; Scott A. Brandt |
| A Null convention logic system for processing NULL convention signals is comprised of interconnected processing elements. NULL convention signals can assume at least a first meaningful value indicating data and a NULL value which has no data significance. Processing elements receive a plurality of NULL convention signals and produce a meaningful output data value when the number of meaningful input data values exceeds a threshold number. The gates assert a NULL output when all inputs are in the NULL state. Processing elements exhibit hysteresis such that, as the number of meaningful input values falls below the threshold number, the element holds a meaningful output value (or a non-data non-NULL value) until all inputs are in the NULL state. The threshold number may be less than the total number of inputs. Groups of elements may be interconnected, and thresholds selected, to perform logic and other processing functions asynchronously on meaningful signal values. | ||||||
| 47 | Asynchronous register for null convention logic systems | US318508 | 1994-10-05 | US5652902A | 1997-07-29 | Karl Fant |
| A NULL convention asynchronous register regulates wavefronts of signals through a NULL convention sequential circuit. The asynchronous register receives a control signal from a downstream circuit when the downstream circuit is ready to receive a new wavefront. Wavefronts alternate between meaningful data and NULL. The asynchronous register further generates a feedback signal to upstream circuits so that upstream circuits generate a wavefront when the sequential circuit is ready to receive the wavefront. Asynchronous registers can be used to create a variety of architectures, and to store data, as in a sequential circuit (state machine). | ||||||
| 48 | High-speed block id encoder circuit using dynamic logic | US580656 | 1995-12-29 | US5635862A | 1997-06-03 | Jeffrey M. Abramson; Bryon G. Conley; Borislav Agapiev |
| A high-speed block id encoder circuit using dynamic logic includes a plurality of input signal lines received from a memory array and a plurality of output signal lines. A first portion of the encoder circuit pre-charges the plurality of output signal lines to a first state. A plurality of transistors coupled together in a single level receives the input signals and discharges the appropriate output signal lines to a second state based on the input signals. The signals produced on the output lines provide an encoded output identifying which one of the plurality of input signal lines is asserted. | ||||||
| 49 | METHOD AND DEVICE FOR PROCESSING SIGNAL | US15926960 | 2018-03-20 | US20180278265A1 | 2018-09-27 | Keisuke TANAKA; Eikoh GOTOH |
| A signal processing device is provided, which includes a pulse compressing module configured to generate a pulse compressed signal obtained by performing pulse compression on a reception signal that is a reflection of a transmission signal transmitted to outside the device, a pseudo signal generating module configured to generate, based on the reception signal, a pseudo signal of which a pseudo main lobe portion corresponding to a main lobe of the pulse compressed signal has a lower signal level than signal levels of pseudo side lobe portions corresponding to side lobes of the pulse compressed signal, and a side lobe removing module configured to remove the pseudo signal from the pulse compressed signal. | ||||||
| 50 | Encoder resolution reduction | US14760897 | 2013-01-18 | US09979412B2 | 2018-05-22 | Keunmo Kang; Slade Culp; Craig Drew Bogli; William A. Veronesi; Daryl J. Marvin |
| One or more embodiments are directed to an encoder configured to output a signal, and a computing device configured to receive the signal from the encoder and generate a reduced resolution version of the signal, the computing device is configured to transmit the reduced resolution version of the signal to a recipient. | ||||||
| 51 | Receiver, sender, method for retrieving an additional datum from a signal and method for transmitting a datum and an additional datum in a signal | US14933349 | 2015-11-05 | US09882579B2 | 2018-01-30 | Dirk Hammerschmidt |
| A receiver includes a receiver circuit to receive a first transition in a first direction, a second transition in a second, different direction after the first transition and a third transition in the first transition after the second transition of a signal. A first time period between the first and third transitions is indicative of a datum to be received. The receiver circuit is also configured to determine a second time period between the first transition and a second transition and to determine an additional datum to be received based at least on the determined second time period between the first and second transitions. Using the determined second time period allows for more information to be received in a reliable manner. | ||||||
| 52 | Method and system for bi-phase mark coding (BMC) decoding | US15364032 | 2016-11-29 | US09866239B1 | 2018-01-09 | Ronald Dean Smith; Xu Zhang; Mikhail Svoiski; Jason Ryan Ferguson |
| Embodiments of methods and systems for BMC decoding are described. In an embodiment, a method for BMC decoding involves performing a unit interval estimation of a BMC encoded bit stream, locating a bit boundary of the BMC encoded bit stream based on the unit interval estimation and a known sequence in a preamble of the BMC encoded bit stream, and measuring a time duration across multiple bit transitions from the bit boundary and decoding the BMC encoded bit stream based on the time duration and the unit interval estimation. | ||||||
| 53 | VECTOR SIGNALING WITH REDUCED RECEIVER COMPLEXITY | US15635012 | 2017-06-27 | US20170294985A1 | 2017-10-12 | Amin Shrokrollahi |
| Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power. | ||||||
| 54 | Digital time converter systems and method | US15199217 | 2016-06-30 | US09641185B1 | 2017-05-02 | Georgios Yorgos Palaskas; Paolo Madoglio; Peter Preyler; Rotem Banin |
| A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal. | ||||||
| 55 | Methods and apparatus to reduce signaling power | US14855115 | 2015-09-15 | US09621385B2 | 2017-04-11 | Timothy Mowry Hollis |
| System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. | ||||||
| 56 | Method and apparatus for valid encoding | US14608319 | 2015-01-29 | US09621303B2 | 2017-04-11 | Ido Bourstein |
| Aspects of the disclosure provide a circuit including an encoding circuit and a valid circuit. The encoding circuit is configured to encode data to be transmitted as signals on a data bus to satisfy a requirement that limits a number of bit transitions between consecutive transmissions. The valid circuit is configured to selectively corrupt the signals not to satisfy the requirement that limits the number of bit transitions between the consecutive transmissions to indicate whether the signals to be transmitted on the data bus constitute valid data or invalid data. | ||||||
| 57 | Devices and methods for pyramid stream encoding | US15041326 | 2016-02-11 | US09602127B1 | 2017-03-21 | Kameran Azadet |
| Devices and methods of reducing quantization noise using a pyramid stream encoder are generally described. Groups of D digital symbols are iteratively computed for a digital signal such that each group of symbols minimizes a norm of a weighted residue vector. The weighted residue vector is formed by applying predetermined weighting coefficients to components of a residue vector. Each component is a difference between a sample of the digital signal and a linear combination of different groups of digital symbols with predefined filter coefficients. The norm of the weighted residue vector evaluated at a rate D times slower than a sampling rate of an output signal. The groups of D digital symbols are provided as the output signal. | ||||||
| 58 | Filter for data rate conversion using feedback with a different frequency | US14834708 | 2015-08-25 | US09553564B1 | 2017-01-24 | Erfan Soltanmohammadi; Kapil Jain |
| Systems, methods, and other embodiments associated with converting an input signal into an output signal with a different sampling rate. In one embodiment, an apparatus includes a feedforward circuit configured to receive the input signal comprised of discrete data samples with the first sampling rate and to generate a first intermediate value based, at least in part, on a feedforward coefficient and the input signal. The apparatus includes a feedback circuit configured to generate a second intermediate value that is based, at least in part, on a feedback coefficient and a predetermined number of previous samples of the output signal. The apparatus includes a signal combiner configured to combine the first intermediate value and the second intermediate value together to interpolate a data sample of the output signal at the second sampling rate. The output signal is a converted form of the input signal at the second sampling rate. | ||||||
| 59 | DATA COMPRESSION METHOD, DATA RESTORATION METHOD, APPARATUSES, AND SYSTEM | US14842514 | 2015-09-01 | US20150372711A1 | 2015-12-24 | Fengping QIN |
| The present invention relates to a data compression method, a data restoration method, apparatuses, and a system. The data compression method includes: acquiring a first digital signal; acquiring a first compressed signal by performing down-sampling processing on the first digital signal, where a sampling frequency of the first compressed signal is not less than a frequency threshold, and the frequency threshold is twice a baseband cut-off frequency of the first digital signal; and sending the first compressed signal by using a transmission format based on the common public radio interface CPRI protocol. Frequency decrease is performed before data is transmitted by using the CPRI protocol, so as to reduce an amount of data to be transmitted by using a CPRI, and improve data transmission efficiency, or, in other words, increase a quantity of RRUs or BBUs that can be supported on per CPRI. | ||||||
| 60 | CONFIGURING SIGNAL-PROCESSING SYSTEMS | US14712539 | 2015-05-14 | US20150332785A1 | 2015-11-19 | Jesper Steensgaard-Madsen; Manideep Gande |
| A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal. | ||||||
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