| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 能够导入/导出设置值的数据处理装置及其控制方法 | CN201310194224.6 | 2013-05-23 | CN103458141A | 2013-12-18 | 冈山典嗣 |
| 本发明提供能够导入/导出设置值的数据处理装置及其控制方法。所述数据处理装置能够在通过导入-导出功能将设置数据传送至其他装置时，减少由字符代码之间的差异导致的字符的编码错乱。存储单元存储所述数据处理装置的设置数据。接收单元接收导出存储在所述存储单元中的设置数据的指令。转换单元把包括在设置数据中的统一码数据，转换为针对所述数据处理装置而设置的语言的字符代码数据。导出单元导出由所述转换单元转换后的所述字符代码数据以及所述统一码数据。 | ||||||
| 2 | 码元转变时钟转码的检错常数 | CN201580063826.5 | 2015-11-24 | CN107005346A | 2017-08-01 | S·森戈库 |
| 公开了用于检测多线接口上的传输中的差错的装置、系统以及方法。一种用于在多线接口上传送数据的方法包括在多线接口上传送数据，包括：获得要在多个连接器上传送的多个比特；将该多个比特转换成码元序列；以及在多个连接器上传送该码元序列。该多个比特中的预定数目的最低有效位可被用于检错。该预定数目的最低有效位可具有与多个差错值中的每一者不同的常数值。影响码元序列中的一个或两个码元的码元差错可以使得预定数目的最低有效位的经解码版本具有作为多个差错值之一的值。 | ||||||
| 3 | 用于存储并检索存储系统中信息的方法和存储装置 | CN201010139364.X | 2003-08-29 | CN101867375A | 2010-10-20 | 杰弗里·S·冈沃尔; 斯蒂芬·J·格罗斯 |
| 本发明揭示用于将数据变换为一可有效地存储于一非易失性存储器中的格式的方法和装置。根据本发明的一个方面，一种用于将一第一数据格式的信息存储到一存储系统中的方法包括：产生与该第一数据格式相关的统计信息，及利用该统计信息将该信息从该第一数据格式变换为一第二数据格式。在将该信息变换为该第二数据格式后，将该信息存储到一存储器中。将该第二数据格式的该信息存储到该存储器中包括：存储一标识一用于将该信息变换为该第二数据格式的变换的标识符。在一实施例中，与存储该第二数据格式的信息相关的成本小于或等于与存储该第一数据格式的信息相关的成本。 | ||||||
| 4 | 半导体装置 | CN201510957520.6 | 2015-12-18 | CN105720834A | 2016-06-29 | 后藤晶子 |
| 本发明得到一种能够降低关断浪涌电压和损耗的半导体装置。在外部端子(P)和外部端子(AC)之间连接有开关元件(Q1)。在外部端子(AC)和外部端子(N)之间连接有开关元件(Q2)。作为AC开关部(SW1)，在外部端子(C)和外部端子(AC)之间反向串联连接有开关元件(Q3、Q4)。作为AC开关部(SW2)，在外部端子(C)和外部端子(AC)之间反向串联连接有开关元件(Q5、Q6)。AC开关部(SW1、SW2)相互并联连接。开关元件(Q1～Q6)被收容于1个模块(M)。 | ||||||
| 5 | 能够导入/导出设置值的数据处理装置及其控制方法 | CN201310194224.6 | 2013-05-23 | CN103458141B | 2015-11-18 | 冈山典嗣 |
| 本发明提供能够导入/导出设置值的数据处理装置及其控制方法。所述数据处理装置能够在通过导入-导出功能将设置数据传送至其他装置时，减少由字符代码之间的差异导致的字符的编码错乱。存储单元存储所述数据处理装置的设置数据。接收单元接收导出存储在所述存储单元中的设置数据的指令。转换单元把包括在设置数据中的统一码数据，转换为针对所述数据处理装置而设置的语言的字符代码数据。导出单元导出由所述转换单元转换后的所述字符代码数据以及所述统一码数据。 | ||||||
| 6 | 数据总线反转设备、系统及方法 | CN200980102231.0 | 2009-01-16 | CN101911034B | 2013-11-06 | 蒂莫西·霍利斯 |
| 本发明揭示多种设备、系统及方法，其操作以根据三种数据总线反转(DBI)算法中的一者来编码在多个通道上传输的数据位。本发明揭示额外的设备、系统及方法。 | ||||||
| 7 | 数据总线反转设备、系统及方法 | CN200980102231.0 | 2009-01-16 | CN101911034A | 2010-12-08 | 蒂莫西·霍利斯 |
| 本发明揭示多种设备、系统及方法，其操作以根据三种数据总线反转(DBI)算法中的一者来编码在多个通道上传输的数据位。本发明揭示额外的设备、系统及方法。 | ||||||
| 8 | 数据存储系统内的符号频率校平 | CN03823356.8 | 2003-08-29 | CN1701513A | 2005-11-23 | 杰弗里·S·冈沃尔; 斯蒂芬·J·格罗斯 |
| 本发明揭示用于将数据变换为一可有效地存储于一非易失性存储器中的格式的方法和装置。根据本发明的一个方面，一种用于将一第一数据格式的信息存储到一存储系统中的方法包括：产生与该第一数据格式相关的统计信息，及利用该统计信息将该信息从该第一数据格式变换为一第二数据格式。在将该信息变换为该第二数据格式后，将该信息存储到一存储器中。将该第二数据格式的该信息存储到该存储器中包括：存储一标识一用于将该信息变换为该第二数据格式的变换的标识符。在一实施例中，与存储该第二数据格式的信息相关的成本小于或等于与存储该第一数据格式的信息相关的成本。 | ||||||
| 9 | 데이터 버스 반전 장치, 시스템 및 방법 | KR1020107015725 | 2009-01-16 | KR1020100105685A | 2010-09-29 | 할리스,티모시 |
| 복수의 채널 상에서 전송되는 데이터 비트를 3가지 데이터 버스 반전(DBI) 알고리즘 중 하나의 알고리즘에 따라 인코딩하도록 동작하는 장치, 시스템 및 방법이 개시된다. 추가의 장치, 시스템 및 방법이 개시된다.
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| 10 | MECHANISM FOR DATA GENERATION IN DATA PROCESSING SYSTEMS | EP16170416.8 | 2016-05-19 | EP3096232B1 | 2018-10-17 | Siegel, Joshua; Welker, James |
| An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data. | ||||||
| 11 | DATA BUS INVERSION APPARATUS, SYSTEMS, AND METHODS | EP09702742.9 | 2009-01-16 | EP2248031B1 | 2018-02-28 | HOLLIS, Timothy |
| Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | ||||||
| 12 | Dynamic decoding of communication between card reader and portable device | EP13195098.2 | 2013-11-29 | EP2838203A2 | 2015-02-18 | Andersson, Fredrik |
The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises preprocessing S1 the received encoded data signal; scanning S2 the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating S3 an actual frequency based on the detected start sequence; interpreting S4, a data block succeeding the start sequence using the assessed actual frequency; and assessing S5 whether to request adjustment S5 of the adjustable encoder clock frequency based on the scanning S2 and/or the interpretation S4. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program.
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| 13 | Concurrent code checker and hardware efficient high- speed I/O having built- in self- test and debug features | EP07250229.7 | 2007-01-19 | EP1814234B1 | 2011-01-12 | Sul, Chinsong; Choi, Hoon; Ahn, Gijung |
| 14 | VERFAHREN ZUR ANPASSUNG DER BITRATE EINES IN EINEM KOMMUNIKATIONSSYSTEM ZU ÜBERTRAGENDEN BITSTROMS UND ENTSPRECHENDE KOMMUNIKATIONSVORRICHTUNG | EP02760159.0 | 2002-09-03 | EP1423935B1 | 2006-11-02 | DÖTTLING, Martin, Walter; RAAF, Bernhard |
| The invention relates to a method for adapting the bit rate in a communication system wherein the bits of the bit stream are punctuated or repeated in such a manner that for a certain respective number (N) of consecutive bits (x) of the bit stream which is to be transmitted, the sum of importances (w) exhibited by the respective bits (x) of the bit stream for the extraction of information containing the respective bit are arranged in a predefined relation to the sum of the reliabilities (v) of the corresponding bits (y) effectively used for transmission so that said bits can be transmit a specific information content after bit rate adaptation has been performed. In particular, a parameter (e), of which for each incoming bit a value (e minus) depending on the importance of the respective bit is subtracted, is used in such a way that if it is greater than zero, the bit is represented as a dotted line. The bit is repeated until the sum of the reliabilities of the corresponding bits actually used for transmission is commensurate with the importance of the respective bit. A parameter (e plus) which is dependent upon the above-mentioned reliabilities of the bits used for the transmission would thus be used. | ||||||
| 15 | MULTI-WIRE SYMBOL TRANSITION CLOCKING SYMBOL ERROR CORRECTION | EP15805713.3 | 2015-11-24 | EP3224977A1 | 2017-10-04 | SENGOKU, Shoichiro |
| Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver. | ||||||
| 16 | Verfahren und Vorrichtung zur Anpassung von fehlerkorrigierenden Kanalkodes an den Leitungskode | EP14151100.6 | 2014-01-14 | EP2773048A1 | 2014-09-03 | Georgiades, Jean; Wiesgickl, Bernhard |
Es wird ein Verfahren zur Übertragung eines Datenpaketes vorgeschlagen. In einem ersten Schritt (301) werden in dem Leitungscode auftretende Fehlermuster ermittelt. In einem zweiten Schritt (302) wird eine Mehrzahl von fehlerkorrigierenden Kanalcodes zum Kodieren der Informationsbits des Datenpakets bestimmt. In einem dritten Schritt (303) werden die Bitpositionen der mittels eines jeweiligen Kanalcodes der Mehrzahl der Kanalcodes kodierten Bits in dem Datenpaket in Abhängigkeit von den ermittelten Fehlermustern bestimmt. Hierdurch können die Fehlererkennung und die Fehlerkorrektur verbessert werden, wodurch sich die a priori erwartete Restfehlerwahrscheinlichkeit vermindert. Ferner wird ein entsprechendes Computerprogrammprodukt sowie eine Vorrichtung zum Übertragen eines Datenpaketes vorgeschlagen.
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| 17 | Concurrent code checker and hardware efficient high- speed I/O having built- in self- test and debug features | EP07250229.7 | 2007-01-19 | EP1814234A3 | 2007-08-08 | Sul, Chinsong; Choi, Hoon; Ahn, Gijung |
Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.
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| 18 | Concurrent code checker and hardware efficient high- speed I/O having built- in self- test and debug features | EP07250229.7 | 2007-01-19 | EP1814234A2 | 2007-08-01 | Sul, Chinsong; Choi, Hoon; Ahn, Gijung |
Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.
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| 19 | SYMBOL FREQUENCY LEVELING IN A DATA STORAGE SYSTEM | EP03749299.8 | 2003-08-29 | EP1532739A1 | 2005-05-25 | GONGWER, Geoffrey, S.; GROSS, Stephen, J. |
| Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format. | ||||||
| 20 | DISPOSITIF DE RECEPTION DE SIGNAUX NUMERIQUES | EP01993978.4 | 2001-11-07 | EP1393450B1 | 2005-05-11 | BOIRIN, Stéphane, Thales Intellectual property; COULEAUD, Jean-Yves, Thales Intellectual Property |
| The invention concerns a device for receiving digital signals in accordance with two different standards passing through the same medium (2, 3, 4) comprising: means for converting (1) logical levels, receiving the digital signals and converting their logical levels into logical levels in accordance with a single standard; means for receiving (7) coded signals in accordance with a first standard, signals derived from the means converting (1) logical levels; means for converting (10) coded signals in accordance with a second standard into coded signals in accordance with the first standard, signals derived from the means converting (1) logical levels; means for transferring (9) signals derived from the means converting (10) of coded signals in accordance with the second standard into coded signals in accordance with the first standard, to the reception means (7) when signals coded in accordance with the second standard are received, or signals derived from the means converting (10) logical levels when signals coded in accordance with the first standard are received. | ||||||
