| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 81 | 고속 광 전송 시스템을 위한 비트 삽입/조작 선로 부호의 부/복호화 장치 | KR1019980048233 | 1998-11-11 | KR1020000031961A | 2000-06-05 | 정희영; 김용진; 진병문; 조경록 |
| PURPOSE: An encoder/decorder of bit insertion/modulation path code for high-speed optical transmission system is provided to minimize the rate of increase of bit by adding 1 bit of insertion bit to information data of m bit and the fluctuation of DC base line. CONSTITUTION: A disparity counter(101) counts a disparity to information data of m bit. An insertion bit generator(102) generates an insertion bit by the disparity of the disparity counter(101). m+1 bit register(103) generates a preliminary encoded m+1 bit block by input information data and the insertion bit. A bit fabrication part(105) fabricates the bit of the preliminary encoded block, so that the disparity of the preliminary encoded block have minimum value. A bit fabrication control part(104) outputs control signal for block reverse by input information data of m bit and disparity. A block reverse part (107) outputs reversed data by performing selective block reverse to the code. A block reverse control part(106) outputs a control signal for block reverse to the block reverse(107) part by disparity. | ||||||
| 82 | 復号化装置、プログラム及び情報伝送システム | JP2014265490 | 2014-12-26 | JP6417937B2 | 2018-11-07 | 浜田 勉; 粟田 恵徳; 宇賀神 淳 |
| 83 | 画像形成装置及びその制御方法、並びにプログラム | JP2012120583 | 2012-05-28 | JP6029321B2 | 2016-11-24 | 岡山 典嗣 |
| 84 | 半導体装置 | JP2014256614 | 2014-12-18 | JP2016119739A | 2016-06-30 | 後藤 晶子 |
| 【課題】ターンオフサージ電圧と損失を低減することができる半導体装置を得る。 【解決手段】外部端子Pと外部端子ACの間にスイッチング素子Q1が接続されている。外部端子ACと外部端子Nの間にスイッチング素子Q2が接続されている。ACスイッチ部SW1として外部端子Cと外部端子ACの間にスイッチング素子Q3,Q4が逆直列接続されている。ACスイッチ部SW2として外部端子Cと外部端子ACの間にスイッチング素子Q5,Q6が逆直列接続されている。ACスイッチ部SW1,SW2は互いに並列接続されている。スイッチング素子Q1〜Q6は1つのモジュールMに収められている。 【選択図】図1 |
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| 85 | Image forming apparatus, control method thereof, and program | JP2012120583 | 2012-05-28 | JP2013244678A | 2013-12-09 | OKAYAMA NORITSUGU |
| PROBLEM TO BE SOLVED: To provide an image forming apparatus that prevents generation of character garbling caused by difference in character codes.SOLUTION: If character string data of a second character code different from a first character code which is a character code of character string data registered in DB 310 for an equipment setting file are to be exported, an image forming apparatus 201 converts the character string data to the second character code. | ||||||
| 86 | Data conversion system | JP2002354495 | 2002-12-06 | JP2004185520A | 2004-07-02 | AOYAMA KAZUYUKI |
| <P>PROBLEM TO BE SOLVED: To facilitate work when carrying out definition of data conversion rules for exchanging data between a plurality of systems by a plurality of operators in construction of a composite system operating the plurality of systems in coordination. <P>SOLUTION: The operators define a first conversion rule for converting a data format of a coordination object system used as an input into a data format of first common data, a second conversion rule for converting the format of the first common data into a format of second common data, and a third conversion rule for converting the format of the second common data into a data format of a coordination object system used as an output. A conversion process of converting the data format of the system used as the input into the data format of the system used as the output is carried out on the basis of the conversion rules. Definition of the conversion rules responding to a role and knowledge of each operator of conversion rule definition is made possible. <P>COPYRIGHT: (C)2004,JPO&NCIPI | ||||||
| 87 | Code converting device for recording code | JP2000332300 | 2000-10-31 | JP2002141804A | 2002-05-17 | ITOI TETSUSHI |
| PROBLEM TO BE SOLVED: To minimize entire circuit scale by minimizing the number of tables to be used for encoding and decoding. SOLUTION: This device is provided with basic tables of 2220 ways less than the 16th power of 2, a reference table having data bit information except the number of continuous bits in the head/end of data bits inputted corresponding to the basic tables and bit conversion control information thereof and a conversion table correspondently having the information of the reference table and information on the number of continuous bits in the head/end of inputted data bits, four reference table addresses are determined at a maximum from the data bits of 16 bits inputted by a conversion table processing part 11 and corresponding to the determined reference table, a reference table processing art 12 calculates a basic table address. Then, a basic table processing part 14 generates plural target channel bits and a 24-channel bit constituting circuit 15 generates 24 channel bits, selectively controls and outputs one of plural bits. | ||||||
| 88 | Encoding and decoding device and its method | JP22468698 | 1998-08-07 | JP2000059227A | 2000-02-25 | FUJIMOTO SHOICHI |
| PROBLEM TO BE SOLVED: To precisely decode a code, which is obtained by decoding such as expressing digital data by a smaller number of bits, to original digital data without deteriorating precision. SOLUTION: The continuing number of 0 is investigated from the lowest order bit of digital data 103, a value obtained by subtracting a number larger than this continuing number of 0 by one from the bit number of data 103 is set to be the number of assigned bits 105 and the bit is assigned from the highest order bit of data 103 according to this number 105. The number of bits reduced by using the number of assigned bits 114 (105) and a low-order bit which is provided with the size and where a highest-order is 1 and the other bits are 0 is generated. This low-order bit is connected to the low-order side of a code 115 (106) to decode to original digital data 117. | ||||||
| 89 | Processing unit and an arithmetic processing method | JP4403397 | 1997-02-27 | JP2856190B2 | 1999-02-10 | UEJIMA YOSHUKI |
| 90 | Arithmetic processing unit and its method | JP4403397 | 1997-02-27 | JPH10242984A | 1998-09-11 | UEJIMA YOSHIYUKI |
| PROBLEM TO BE SOLVED: To simplify a DC bias suppressing circuitry for transmitting data. SOLUTION: A 1st counter A16 for executing the operation of a whitener encoder executes up/down counting only by +3, +1, -1, or -3 in accordance with judgment whether 2-bit symbol data in an n-bit section partitioned by two n/2 bit shift registers 13a, 13b are '10', '11', '01' or '00' and a 2nd counter B17 executes up/down counting only by +3, +1, -1, or -3 in accordance with judgment whether already sent 2-bit symbol data are '10', '11', '01', or '00'. The inversion availability of transmitting data is judged by judging the most significant bit of each counter by a comparator 18. When both the code bits of the counters 16, 17 are '0' or '1', the transmitting data are inverted, and when one of two code bits is '0' and the other is '1', inversion is not executed. Each of bit stuff circuits 14a, 14b inserts one-bit data into the transmitting data in each n/2 bits. COPYRIGHT: (C)1998,JPO | ||||||
| 91 | JPS6144428B2 - | JP6311180 | 1980-05-12 | JPS6144428B2 | 1986-10-02 | OIKAWA MASANORI |
| 92 | JPS617064B2 - | JP2466178 | 1978-03-03 | JPS617064B2 | 1986-03-04 | MIZUKURA SUSUMU; KOBAYASHI KAZUHIKO |
| 93 | Code converter | JP7162981 | 1981-05-13 | JPS57186861A | 1982-11-17 | OKAMOTO EIJI |
| PURPOSE:To shorten a processing time by a comparatively small scale, by constituting a code converter of a data cycling device, a selective multiplier, a remainder device and a square device. CONSTITUTION:Input data sequences a0, a1, a2, ... applied to an input terminal 101 are applied to a data cycling device 103 and are outputted cyclically only for a prescribed time. A selective multiplier 104 selectively switches to one of a data from the cycling device 103 as it is, or the product of the data of the cycling device 103 and a data of a square device 106, or the data of the square device as it is, and provides it to a remainder device 105. The remainder device 105 converts the data from the multiplier 104 to the remainder divided by a positive integer (n). Also, the square device 106 converts the data from the remainder device 105 to a data squared by making (n) a root, and provides it to the multiplier 104. As a result, the remainder obtained by dividing a0<m>, a1<m>, a2<m>, ... (m is a positive integer) by (n) is outputted to an output terminal 102. In this way, this code converter is constituted like a pipeline, therefore, its processing time is shortened to log2m or so of the processing time of the multiplier. | ||||||
| 94 | Communication controller providing code converting function | JP6311180 | 1980-05-12 | JPS56158553A | 1981-12-07 | OIKAWA MASANORI |
| PURPOSE:To simplify the constitution of character processing and to reduce the load of processors, by installing a code conversion table between a serial-parallel conversion section and a character processing section according to each communication line. CONSTITUTION:In communication controller allocating a plurality of data communication lines, code conversion sections 220-1-220-n are provided according to each communication line between serial conversion sections 210-1-210-n and a character processing section 230. Thus, if the code system in a system can adopt only the same one to all the lines, the character processing section 230 can make the character processing of sole code system. Further, if the code system of each line cannot be the same, the transmission control processing of the character processing section is made common with the information stored in the additional control field after the code conversion to reduce the load. | ||||||
| 95 | Character conversion system | JP4844380 | 1980-04-11 | JPS56144654A | 1981-11-11 | HAYAKAWA EI; EGUCHI MASATO; NUMAZAWA KAZUMI |
| PURPOSE:To reconvert output converted character B to character A while securing the continuity of the character, and to detect character A rapidly by comparing patterns of character inputted by (m) bits together at every time, by (m) bits together at every time. CONSTITUTION:An eight-bit character is inputted from input line 11 and in memory 12, on the other hand, coordinate relations among patterns A, B and C are stored. Comparator 13 makes six-bit comparisons between the both to discriminate identical pattern A (e.g. pattern A.1). Once the coincidence is discriminated as many times as prescribed, a signal is sent to control circuit 14, which discriminates pattern A (e.g. pattern A.3) detected finally by comparator 13 and then reads out of memory 12 the pattern B.5 that corresponds to pattern A.5 to follow it next. | ||||||
| 96 | Code conversion circuit | JP17255179 | 1979-12-28 | JPS5696553A | 1981-08-04 | INOUE KOUICHI; MURATA EIICHIROU; YAMANE MANABU; NAKANISHI TETSUAKI |
| PURPOSE:To realize the combination of a number of codes with a comparatively simple circuit, by using the output of an exclusive logical sum gate for the address designation of memory via a shift register and decoder. CONSTITUTION:An input signal is fed to one input of an exclusive logical sum gate 1, the output is fed to a 8-bit shift register 2, and the output of, e.g., 3 prestages of the register 2 is fed to a decoder 3. Further, the output decoded into 8 signals designates the address of a bit memory 4, and the output of the memory 4 is fed to another input of the gate 1. Thus, the combination of codes in 14336 ways can be made. | ||||||
| 97 | Code converter | JP15843578 | 1978-12-25 | JPS5586242A | 1980-06-28 | MORIYAMA KAZU; KIOGAWA TAKAO |
| PURPOSE:To make it possible to send out an output of conversion of an input Roman character input into a katakana character (Japanese syllabary) code, by providing a code converter with a character converting function between katakana characters and Roman characters. CONSTITUTION:To input characters by a five-unit code terminal equipment, a shift code, discrimination code for discriminating whether an alphabetic document is Japanese or English, and the alphabetic document or symbols are inputted in sequence following a function key. A code conveter stores the position of the shift code first and decides upon letters and numbers or symbols to extract them respectively while storing them. Next, a decision on whether letter codes are outputted as the English writing is or Roman characters are converted into katakana characters is made and after Roman characters are converted into katakana codes, six- unit codes are outputted. Those extracted letter, characters and symbols are outputted by a six-unit code terminal equipment. Further, Roman characters which can not be converted into katakana codes are outputted as they are and as to characters disagreeing with conversion rules, error codes are outputted. | ||||||
| 98 | Error correcting method and system for facsimile transmission | JP9520877 | 1977-08-10 | JPS5337313A | 1978-04-06 | REIMON JIORUJIYU SHIYAI; PIITAA HOMAN; URUFU ROOTOGORUTO |
| 99 | JPS52339B1 - | JP5910971 | 1971-08-06 | JPS52339B1 | 1977-01-07 | |
| 100 | JPS5144049B2 - | JP11223072 | 1972-11-10 | JPS5144049B2 | 1976-11-26 | |
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