Code conversion circuit |
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| 申请号 | JP17255179 | 申请日 | 1979-12-28 | 公开(公告)号 | JPS5696553A | 公开(公告)日 | 1981-08-04 |
| 申请人 | Matsushita Electric Ind Co Ltd; | 发明人 | INOUE KOUICHI; MURATA EIICHIROU; YAMANE MANABU; NAKANISHI TETSUAKI; | ||||
| 摘要 | PURPOSE:To realize the combination of a number of codes with a comparatively simple circuit, by using the output of an exclusive logical sum gate for the address designation of memory via a shift register and decoder. CONSTITUTION:An input signal is fed to one input of an exclusive logical sum gate 1, the output is fed to a 8-bit shift register 2, and the output of, e.g., 3 prestages of the register 2 is fed to a decoder 3. Further, the output decoded into 8 signals designates the address of a bit memory 4, and the output of the memory 4 is fed to another input of the gate 1. Thus, the combination of codes in 14336 ways can be made. | ||||||
| 权利要求 | |||||||
| 说明书全文 | |||||||
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