| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | Demodulation apparatus and method | JP23759398 | 1998-08-24 | JP4009798B2 | 2007-11-21 | 俊之 中川 |
| 62 | The same level of the symbol frequency in the data storage system | JP2004532020 | 2003-08-29 | JP2005537551A | 2005-12-08 | ジェイ． グロス，ステファン; エス． ゴングウァー，ジェフリー |
| データを、不揮発性メモリに効率良く格納できるフォーマットに変換する方法および装置に関する。 本発明の１つの態様によれば、第１のデータフォーマットの情報をメモリシステムに格納する方法には、第１のデータフォーマットに関連する統計値を生成するステップと、その統計値を用いて、第１のデータフォーマットから第２のデータフォーマットへ情報を変換するステップとが含まれる。 この情報は、第２のデータフォーマットに変換されるとすぐに、メモリの中へ格納される。 第２のデータフォーマットで当該情報をメモリに格納するステップには、当該情報を第２のデータフォーマットに変換するのに用いる変換値を特定する識別子を格納するステップが含まれる。 一実施形態では、第２のデータフォーマットの情報を格納する関連コストは、第１のデータフォーマットの情報を格納する関連コスト以下である。 | ||||||
| 63 | Whole processing device for data | JP2003425525 | 2003-12-22 | JP2004206721A | 2004-07-22 | LEHONGRE DENIS |
| PROBLEM TO BE SOLVED: To reduce an operation time in the case of processing a large number of data. SOLUTION: This device is a digital data processor, more specifically, a device for reading the maximum value or the minimum value of data belonging to a set of 2 n codes, an order relation is established and each code has a rank R constituted of 0 to 2 n-1, respectively in the set. The device is a conversion circuit for each piece of digital data processed for generating the conversion of binary digits constituted of 2 n binary elements T[x] having X=1 to 2 n-1, T[2 n-1]T[2 n-2] T[x] to T[2] T[1] and is provided with the one in which T(x)=0 when X is absolutely larger than R and T(x)=1 when X is smaller than or equal to R here. The circuit for executing digital processing receives the result of this conversion. COPYRIGHT: (C)2004,JPO&NCIPI | ||||||
| 64 | Demodulator, its method and serving medium | JP23759398 | 1998-08-24 | JP2000068850A | 2000-03-03 | NAKAGAWA TOSHIYUKI |
| PROBLEM TO BE SOLVED: To reduce propagation of an error with a simpler configuration on the occurrence of a bit shift error. SOLUTION: An error code/restrain length discrimination section 21, a minimum run continuous limit code detection section 22, and a minimum run.maximum run restrain code detection section 23 of this demodulator specify a restrain length of a code with a prescribed length including an error and inverse conversion sections 26-1-26-4 and an error data demodulation table 25 demodulate the code based on the specified restrain length. COPYRIGHT: (C)2000,JPO | ||||||
| 65 | Circuit and method for signal transmission | JP6648898 | 1998-03-17 | JPH11266158A | 1999-09-28 | MIKI YOSHIO |
| PROBLEM TO BE SOLVED: To reduce the maximum value and the average of the number of bits which change at the sometime, in the transmission of a logical signal. SOLUTION: This device is equipped with a logical circuit 100, which converts a logical signal of n bits into m pairs (m is an integer equal to one or larger) of a group of logical signals, where only k bits (k is an integer equal to one or larger) change, a transmission line for transmitting the m pairs of logical signals, where only the k bits change, and a logical circuit 103 which converts the m pairs of logical signals, where only k bits change into a logical signal of the original n bits. Thus, for the maximum value of the number of changing bits has the product of k and m as an upper limit. Also, when the product of k and m is less than n/2, the average number of changing bits can be reduced also. COPYRIGHT: (C)1999,JPO | ||||||
| 66 | JPH035101B2 - | JP7162981 | 1981-05-13 | JPH035101B2 | 1991-01-24 | OKAMOTO EIJI |
| 67 | JPS6132859B2 - | JP4844380 | 1980-04-11 | JPS6132859B2 | 1986-07-30 | HAYAKAWA EI; EGUCHI MASATO; NUMAZAWA KAZUMI |
| 68 | JPS6112424B2 - | JP11073980 | 1980-08-12 | JPS6112424B2 | 1986-04-08 | KITAGAWA AIKO |
| 69 | Interface device | JP11073980 | 1980-08-12 | JPS5735451A | 1982-02-26 | KITAGAWA AIKO |
| PURPOSE:To make the data conversion to a different code and the switching of a plurality of input and output switching with a program on a central processing device, by providing a switch code in a received electric message, in an interface device between a central processing device and a terminal device. CONSTITUTION:In a received electric messages (1)-(4), the types of an output device outputting the succeeding data 2 and the data conversion before the output is designated by an output designation switch code 1, and an input designation switch code 3 designates the input device inputting the data to be transmitted to a central processing device and the types of the data conversion to the inputted data. When the device is in reception state, a transmission control section 5 transmits the received electric message to a switch code detection section 6 and the result of the detection is registrated on an electric message control table 7. An electric message control section 8 makes the data conversion of the received data according to a table 7 and outputs the data via an output interface section 10 corresponding to the registrated output device. In the transmission state, the data is inputted from a designated input device with the table 7 and the electric message control section 8 and transmitted after the data conversion. | ||||||
| 70 | Transmission system of serial binary code | JP14259179 | 1979-11-02 | JPS5666950A | 1981-06-05 | YAMAMOTO MASAHARU |
| PURPOSE:To reduce the amount of code setting work, by selecting arbitrary m-sets out of 2<n> types of n-digit serial binary codes and transmitting them serially in the designated order. CONSTITUTION:A 4-digit serial binary code generating circuit FC repetitively outputs 4-bit signals to 16 output terminals O-F based on the clock CL from the clock pulse generating circuit CG. A multiplexer Mx transmits the signal in 4-bit fed to 16 sets of input terminals 0'-15' based of the selection signal sequentially in serial via a flip-flop FF. Accordingly, by arbitrarily connecting the input terminals 0'-15' to the output terminals O-F of FC, in case of Figure, the binary codes having 64-bit arbtrary pulse patterns can be transmitted. | ||||||
| 71 | Code converter | JP15843478 | 1978-12-25 | JPS5586241A | 1980-06-28 | MORIYAMA KAZU; KIOGAWA TAKAO |
| PURPOSE:To make it possible to send an output of conversion of an input katakana character (Japanese syllabary) code into a Roman character, by providing a code converter with a function of character conversion between katakana characters and Roman characters. CONSTITUTION:From an input of a six-unit code, the position of a shift code is detected first and stored. Next, a decision on an alphabet and numeral or a symbol and katakana character which the input is in the form of is made by the shift position and in case of a katakana character, the input is converted into a Roman character. When the katakana input has a ''p''-sound in this case, it is keyed in with the ''p''-sound symbol, i.e. a semi-voiced sound attached to a katakana character. Those extracted alphabet, numeral, symbol, and Roman character are converted by a terminal equipment and outputted. In this case, the shift code is outputted prior to the transmission of various codes. Further, in case that a code which can not be converted into a Roman character is inputted, it is detected to output a unit code at the terminal side as a space code. | ||||||
| 72 | Data transmission system | JP2466178 | 1978-03-03 | JPS54117604A | 1979-09-12 | MIZUKURA SUSUMU; KOBAYASHI KAZUHIKO |
| PURPOSE:To transmit efficiently and exactly all combination data of eight bits as data other than transmission control characters by normal transmission control procedures, by dividing eight-bit data groups into six-bit data groups and transmitting and receiving them. CONSTITUTION:Information in memory controller 11 is sent to line 13 through communication controller 12, and information from line 13 is inputted to controller 11. At a transmission time, continuous three digits of eight-bit information is divided into four digits of six-bit information befoer transmission, and two-bit redundant bits are added to divided six-bit information, and information is transmitted as a eight-bit code other than transmission control characters. At a receiving time, two- bit redundant bits are removed from the recieved continuous four-digit eight-bit code to obtain four-digit six-bit information, and four-digit six-bit information of the output is converted to three-digit eight-bit information. | ||||||
| 73 | Electronic communication terminal system | JP8043976 | 1976-07-08 | JPS5210019A | 1977-01-26 | MARUKOMU MAKOOREI |
| A system for the transmission and reception of complex codes which provides a simple means for selection by an operator of the item to be encoded and transmitted. The invention allows the transmitted signal to be decoded and to be shown visually without requiring any assistance from an operator. Standard electrical and electronic components are used in the equipment of the invention. This invention is especially useful for signalling messages in Chinese or Japanese text, which both have a large number of characters and present difficulties in transmission and reception with conventional teleprinter machines. | ||||||
| 74 | JPS5032582B1 - | JP7246169 | 1969-09-12 | JPS5032582B1 | 1975-10-22 | |
| 75 | JPS4953313A - | JP8257273 | 1973-07-20 | JPS4953313A | 1974-05-23 | |
| 76 | 내장된 자가-테스트 및 디버그 특징을 갖는 동시 코드검사기 및 하드웨어 효율적인 고속 Ｉ/Ｏ | KR1020070006687 | 2007-01-22 | KR101423328B1 | 2014-07-24 | 술,친송; 최,훈; 안,기정 |
| 고속 입/출력 시스템들에서 오류들을 테스트하기 위한 방법, 디바이스 및 시스템이 개시된다. 이 시스템 및 디바이스는, 패킷들을 포함하는 데이터 스트림의 동적 속성들 및 데이터 패킷 정적 속성들을 통해 부호화된 데이터 패킷들 내의 오류들을 검사하는 C3(concurrent code checker)를 포함할 수 있다. 이 방법은 패킷들을 포함하는 데이터 스트림의 동적 속성들 및 데이터 패킷 정적 속성들을 사용하여 무효의 부호화된 패킷들을 검출하는 단계를 수반할 수 있다. 무시(don't care)의 조건들을 사용하여 C3 로직의 설계를 최적화하는 방법이 개시되며, C3 회로는 감소된 로직 요소 및 반도체 면적 필요조건을 가진다. 고속 입/출력 시스템, 동시 코드 검사기, 무시(don't care) | ||||||
| 77 | 데이터 버스 반전 장치, 시스템 및 방법 | KR1020107015725 | 2009-01-16 | KR101125975B1 | 2012-03-20 | 할리스,티모시 |
| 복수의 채널 상에서 전송되는 데이터 비트를 3가지 데이터 버스 반전(DBI) 알고리즘 중 하나의 알고리즘에 따라 인코딩하도록 동작하는 장치, 시스템 및 방법이 개시된다. 추가의 장치, 시스템 및 방법이 개시된다.
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| 78 | 통신 시스템에서의 채널 부호화 장치 및 방법 | KR1020100031147 | 2010-04-05 | KR1020110111856A | 2011-10-12 | 양현구; 정홍실; 명세호; 김재열 |
| 본 발명은 파운틴 부호를 사용하여 부호화할 전체 소스 심볼들 중 적어도 하나의 소스 심볼에 의해 하나의 부호화 심볼을 생성할 때, 상기 전체 소스 심볼들을 적어도 한번씩 사용하여 최소 개수의 부호화 심볼들을 생성하는 통신 시스템에서의 부호화 장치 및 방법을 제안한다.
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| 79 | 내장된 자가-테스트 및 디버그 특징을 갖는 동시 코드검사기 및 하드웨어 효율적인 고속 Ｉ/Ｏ | KR1020070006687 | 2007-01-22 | KR1020070077141A | 2007-07-25 | 술,친송; 최,훈; 안,기정 |
| A C3(Concurrent Code Checker) and a hardware efficient HSIO(High Speed Input/Output) having a built-in self-test and debug features are provided to optimize design of the C3 and reduce area for logic elements and semiconductors required for C3 circuit by using 'don't care' conditions. A hardware efficient HISO having a built-in self-test and debug features includes a serial-parallel converter(102), a decoder(106), and a C3(104). The serial-parallel converter(102) receives a high speed data transmission encoded by converting data in serial and is coupled to the decoder(106) and the C3(104). The decoder(106) decodes encoded data packets received from the serial-parallel converter(102). The C3(104) receives the encoded data packets from the serial-parallel converter(102) and inspects the data packets by using code book and a DC/RD specification logic formula while encoding the encoded data packets. | ||||||
| 80 | 니블 반전 부호 활용 방법 및 그 장치 | KR1020000059462 | 2000-10-10 | KR100384886B1 | 2003-05-22 | 이범철; 손종무; 최은창; 박권철 |
| A method for using a nibble(partial bits of word) inversion code in a network system includes the steps of: a) adding 1 redundancy bit to n bit source data and generating a pre-code, n being an even number of 2 or over; b) deciding the number of transitions in the generated pre-code; c) determining the pre-code as a code word if the number of transitions in the pre-code is greater than or equal to 1+n/2 in a deciding result; d) inverting alternate bits including the redundancy bit among bits constructing the pre-code and generating the code word, if the number of transitions in the pre-code is less than n/2 in the deciding result; e) determining the pre-code as the code word in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is not an in-band signaling and not a special word in the deciding result; and f) inverting the nibble among the bits constructing the pre-code and generating the code word, in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is an in-band signaling or is a special word in the deciding result. | ||||||
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