Dispositif de traitement de données numériques, et notamment d'extraction de maximum ou de minimum parmi des valeurs appartenant à un ensemble de 2ⁿ codes dans lequel une relation d'ordre est établie et pour lequel chacune desdites données dispose d'un rang R compris entre 0 et 2ⁿ-1, le circuit étant caractérisé en ce qu'il comporte :

• un circuit de conversion pour chaque donnée numérique à traiter afin de générer une transformée qui est un nombre binaire composé de 2ⁿ-1 éléments binaires T[x] avec x = 1 à 2ⁿ-1 :$${\text{T[2}}^{\text{n}}{\text{-1] T[2}}^{\text{n}}\text{-2] ...T[x] ... T[2] T[1]}$$ Dans lequel on a T(x) = 0 lorsque x est strictement supérieur à R et T(x)=1 lorsque x est inférieur ou égal à R,
• des circuits recevant le résultat desdites conversion et effectuant un traitement numérique sur ledit résultat.

An encoder/decoder architecture for buses, capable of minimizing power consumption by reducing the switching activity, generates, from an input information value (b^(t)) relating to a given instant (t), a corresponding current output value (B^(t)) on encoded bus lines relating to the same given instant. The architecture comprises storage means (10, 12) for storing respective preceding values of input information (b^(t-1)) and output information (B^(t-1)) relating to instants preceding the aforesaid given instant (t). A prediction block (P) generates, from the preceding value of input information, an estimate (b^^(t)) of the current input information value. A decorrelation block (D) decorrelates the current input information value (b^(t)) with respect to the said estimate. Finally, a selection block (S) selects as the current output value (B^(t)) one out of the current input information value (b^(t)), the result of the decorrelation (e^(t)) implemented by the decorrelation block (D) or the preceding output value (B^(t-1)) .

An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.

The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises preprocessing S1 the received encoded data signal; scanning S2 the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating S3 an actual frequency based on the detected start sequence; interpreting S4, a data block succeeding the start sequence using the assessed actual frequency; and assessing S5 whether to request adjustment S5 of the adjustable encoder clock frequency based on the scanning S2 and/or the interpretation S4. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program.

A channel encoding method is disclosed, which comprises dk-encoding and NRZI precoding, the output of which obeys a repeated minimum transition runlength constraint and is FSM decodable with a given lookahead depth. Occurrences of RMTR violating critical bit sequences are replaced by same length replacement sequences containing extended zero runs; and the FSM decodability with the given lookahead depth is achieved by using only those replacement sequences that are decodable with the given lookahead depth. A pertaining FSM channel decoding method and channel decoding apparatus are disclosed.

Method for transmitting information in a communication system, especially a mass communication system, comprising a number of transmitting stations, a number of receiving stations and transmission links between said transmitting and receiving stations.

Information in a natural language is supplied at the input of the transmitting stations and said information is delivered in a natural language at the output of said receiving stations. In said transmitting stations the information is translated from the natural language into esperanto, whereafter the translated information is encoded in a suitable code for transmission to said receiving stations. Therein the information is translated from the encoded esperanto into the same or another natural language.