| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Electric telegraphy. | US1905244189 | 1905-02-04 | US793037A | 1905-06-20 | KITSEE ISIDOR |
| 182 | MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD | US15693585 | 2017-09-01 | US20180152207A1 | 2018-05-31 | Daiki WATANABE |
| A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets rm (rm is a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the rm) symbols of the rm symbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values. | ||||||
| 183 | Capacitor Order Determination in An Analog-to-Digital Converter | US15483046 | 2017-04-10 | US20170250699A1 | 2017-08-31 | Thomas Fuchs; Rudiger Kuhn; Bernhard Wolfgang Ruck |
| An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system. | ||||||
| 184 | Path encoding and decoding | US15358909 | 2016-11-22 | US09667271B2 | 2017-05-30 | Frederic J. Bauchot; Marc Joel Herve Legroux |
| This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters. | ||||||
| 185 | Digital encoding of parallel busses to suppress simultaneous switching output noise | US14563485 | 2014-12-08 | US09632883B2 | 2017-04-25 | Robert P. Masleid; Don Draper; Venkat Krishnaswamy; Paul Loewenstein |
| An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality. | ||||||
| 186 | Path encoding and decoding | US15184306 | 2016-06-16 | US09577670B2 | 2017-02-21 | Frederic J. Bauchot; Marc Joel Herve Legroux |
| This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters. | ||||||
| 187 | Semiconductor device | US14844861 | 2015-09-03 | US09577627B2 | 2017-02-21 | Akiko Goto |
| First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources. A first switching element is connected between the first and fourth external terminals. A second switching element is connected between the fourth and second external terminals. A first AC switch unit includes third and fourth switching elements connected in inverse series between the third and fourth external terminals. A second AC switch unit includes fifth and sixth switching elements connected in inverse series between the third and fourth external terminals. The first and second AC switch units are connected in parallel. The first and second switching elements and the first and second AC switch units are incorporated in one module. | ||||||
| 188 | DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE | US14563485 | 2014-12-08 | US20160164539A1 | 2016-06-09 | Robert P. Masleid; Don Draper; Venkat Krishnaswamy; Paul Loewenstein |
| An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality. | ||||||
| 189 | Encoding payloads according to data types while maintaining running disparity | US14170852 | 2014-02-03 | US09270415B2 | 2016-02-23 | Aviv Salamon; Eyran Lida |
| Methods and systems for encoding frames while maintaining bounded running disparity, including: encoding the headers of the frames utilizing a first line-code; selecting the first line-code and a second line code for encoding first and second payloads of first and second frames, respectively, based on first and second data types of first and second data comprised in the first and second payloads, respectively; encoding the first and second payloads utilizing the first and second line-codes, respectively; and transmitting the first and second frames over a communication channel characterized by first and second channel conditions, respectively. The second line-code has a minimal Hamming distance lower than that of the first line-code, and the differences between the first and second channel conditions are not enough for selecting the second line-code instead of the first line-code for encoding the second payload. | ||||||
| 190 | Efficient two-stage asynchronous sample-rate converter | US14043509 | 2013-10-01 | US09258011B2 | 2016-02-09 | J. William Whikehart; David P. Stewart; Dave Lavacek |
| Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter. | ||||||
| 191 | Data processing apparatus that enables import/export of setting value, control method therefor, and storage medium storing control program therefor | US14561624 | 2014-12-05 | US09237251B2 | 2016-01-12 | Noritsugu Okayama |
| A data processing apparatus that is capable of reducing the garbling of characters caused by the difference among the character codes when setting data are transferred to another apparatus by the import-export function. A storage unit stores setting data for the data processing apparatus. A receiving unit receives an instruction for exporting the setting data stored in the storage unit. A converting unit converts Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus. An export unit exports the character code data converted by the converting unit and the Unicode data. | ||||||
| 192 | Encoding payloads according to data types while maintaining running disparity | US14170852 | 2014-02-03 | US20150222388A1 | 2015-08-06 | Aviv Salamon; Eyran Lida |
| Methods and systems for encoding frames while maintaining bounded running disparity, including: encoding the headers of the frames utilizing a first line-code; selecting the first line-code and a second line code for encoding first and second payloads of first and second frames, respectively, based on first and second data types of first and second data comprised in the first and second payloads, respectively; encoding the first and second payloads utilizing the first and second line-codes, respectively; and transmitting the first and second frames over a communication channel characterized by first and second channel conditions, respectively. The second line-code has a minimal Hamming distance lower than that of the first line-code, and the differences between the first and second channel conditions are not enough for selecting the second line-code instead of the first line-code for encoding the second payload. | ||||||
| 193 | Maintaining running disparity while utilizing different line-codes | US14170826 | 2014-02-03 | US20150222293A1 | 2015-08-06 | Eyran Lida; Aviv Salamon |
| Methods and systems for encoding a frame utilizing at least two line-codes having different minimal Hamming distances. The method includes maintaining over the frame absolute value of running disparity lower than or equal to K, while: encoding a first part of the frame utilizing a first line-code having a binary code word length N′ and a minimal Hamming distance D′; and encoding a second part of the frame utilizing a second line-code having a binary code word length N″ and a minimal Hamming distance D″ lower than D′. Where the value of K is lower than both N′/2 and N″/2. | ||||||
| 194 | EFFICIENT TWO-STAGE ASYNCHRONOUS SAMPLE-RATE CONVERTER | US14043509 | 2013-10-01 | US20150091743A1 | 2015-04-02 | J. Willliam Whikehart; David P. Stewart; Dave Lavacek |
| Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter. | ||||||
| 195 | DATA PROCESSING APPARATUS THAT ENABLES IMPORT/EXPORT OF SETTING VALUE, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR | US14561624 | 2014-12-05 | US20150085328A1 | 2015-03-26 | Noritsugu Okayama |
| A data processing apparatus that is capable of reducing the garbling of characters caused by the difference among the character codes when setting data are transferred to another apparatus by the import-export function. A storage unit stores setting data for the data processing apparatus. A receiving unit receives an instruction for exporting the setting data stored in the storage unit. A converting unit converts Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus. An export unit exports the character code data converted by the converting unit and the Unicode data. | ||||||
| 196 | TAPE HEADER FORMAT HAVING EFFICIENT AND ROBUST CODEWORD INTERLEAVE DESIGNATION (CWID) PROTECTION | US14010387 | 2013-08-26 | US20150058696A1 | 2015-02-26 | Roy D. Cideciyan; Robert A. Hutchins; Thomas Mittelholzer; Keisuke Tanaka |
| In one embodiment, a system for providing header protection in magnetic tape recording is adapted to write a codeword interleave (CWI) set on a magnetic tape including a plurality of CWIs equal to a number of tracks, wherein a data set includes a plurality of CWI sets, provide a CWI set header for the CWI set, the CWI set header including a CWI header for each CWI in the CWI set, each CWI header including at least a CWI Designation (CWID) which indicates a location of the CWI within the data set, calculate or obtain CWID parity for all CWIDs in the CWI set header, the CWID parity including error correction coding (ECC) parity, and store the CWID parity to one or more fields which are repeated for each CWI header in the CWI set header without using reserved bits in the CWI set header to store the CWID parity. | ||||||
| 197 | Data processing apparatus that enables import/export of setting value, control method therefor, and storage medium storing control program therefor | US13901685 | 2013-05-24 | US08933827B2 | 2015-01-13 | Noritsugu Okayama |
| A data processing apparatus that is capable of reducing the garbling of characters caused by the difference among the character codes when setting data are transferred to another apparatus by the import-export function. A storage unit stores setting data for the data processing apparatus. A receiving unit receives an instruction for exporting the setting data stored in the storage unit. A converting unit converts Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus. An export unit exports the character code data converted by the converting unit and the Unicode data. | ||||||
| 198 | Data Bus Inversion Apparatus, Systems, and Methods | US12577276 | 2009-10-12 | US20100026533A1 | 2010-02-04 | Timothy Hollis |
| Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | ||||||
| 199 | Data bus inversion apparatus, systems, and methods | US12015311 | 2008-01-16 | US07616133B2 | 2009-11-10 | Timothy Hollis |
| Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | ||||||
| 200 | DC free code design with state dependent mapping | US10978676 | 2004-11-01 | US20050151674A1 | 2005-07-14 | Kinhing Tsang |
| A codeword for use in a communication channel is provided. A first segment of the codeword includes a plurality of bits having a running digital sum (RDS) and a second segment includes a plurality of bits based on the RDS of the first segment. | ||||||
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