| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 121 | Data bus inversion apparatus, systems, and methods | US13292276 | 2011-11-09 | US08766828B2 | 2014-07-01 | Timothy Hollis |
| Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | ||||||
| 122 | Data Bus Inversion Apparatus, Systems, and Methods | US13292276 | 2011-11-09 | US20120056762A1 | 2012-03-08 | Timothy Hollis |
| Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | ||||||
| 123 | Data conversion system | US10452166 | 2003-05-30 | US07644357B2 | 2010-01-05 | Kazuyuki Aoyama |
| A worker defines a first conversion rule to convert data in a data format of a cooperative operation objective system as an input into data in a data format of first common data, a second conversion rule to convert data in the format of the first common data into data in a data format of a second common data, and a third conversion rule to convert data in the data format of the second common data into data in a data format of a cooperative operation objective system as an output. According to the rules, conversion processing is executed to convert data in the data format of the input system into data in the data format of the output system. | ||||||
| 124 | Power efficient, high bandwidth communication using multi-signal-differential channels | US10923111 | 2004-08-20 | US07358869B1 | 2008-04-15 | Donald M. Chiarulli; Steven P. Levitan |
| A low-power, area and pin efficient signaling alternative to serial differential links used for chip-to-chip, backplane, optical and other signaling applications. The multi-bit differential signaling (MBDS) generally comprises a driver and link termination network design coupled with a coding system based on n choose M (nCm) coding. MBDS has comparable electrical characteristics to conventional low-voltage differential signaling (LVDS) and is fully compatible with existing LVDS receivers in point-to-point and multi-point bus topologies. However, MBDS uses up to 40% less power, with up to 33% fewer I/O pads than equivalent LVDS links. | ||||||
| 125 | Symbol frequency leveling in a storage system | US11201007 | 2005-08-09 | US07266026B2 | 2007-09-04 | Geoffrey S. Gongwer; Stephen J. Gross |
| Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format. | ||||||
| 126 | State modulation method and apparatus for inserting state control codes | US11244593 | 2005-10-06 | US07102546B2 | 2006-09-05 | Chang-Po Ma; Yung-Chi Yang; Che-Kuo Hsu; Sun-How Jiang |
| A state modulation method and an apparatus for inserting state control codes are provided. To overcome the problems of inefficient control on direct current and low frequency component in conventional state modulation techniques, the disclosed method inserts state control codes in a state modulation method to increase the probability for selection. With multi-level characteristics, the inserted state control codes can provide a plurality of sets of different signals for selection during coding. Thereby, the direct current and low frequency components can be well controlled. | ||||||
| 127 | DC free code design with state dependent mapping | US10978676 | 2004-11-01 | US07088268B2 | 2006-08-08 | Kinhing Paul Tsang |
| A codeword for use in a communication channel is provided. A first segment of the codeword includes a plurality of bits having a running digital sum (RDS) and a second segment includes a plurality of bits based on the RDS of the first segment. | ||||||
| 128 | Symbol frequency leveling in a storage system | US10230657 | 2002-08-29 | US06941412B2 | 2005-09-06 | Geoffrey S. Gongwer; Stephen J. Gross |
| Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format. | ||||||
| 129 | Device for receiving digital signals | US10416009 | 2001-11-07 | US06853216B2 | 2005-02-08 | Stéphane Boirin; Jean-Yves Couleaud |
| The invention relates to a device for receiving digital signals on the basis of two different standards conveyed on the same medium. A logic-level conversion device receives the digital signals and converts their logic levels into logic levels on the basis of a single standard. Reception is provided for receiving signals coded on the basis of a first standard, which signals are output by the logic-level conversion device. Signals coded on the basis of a second standard are converted into signals coded on the basis of the first standard, which signals are output by the logic-level conversion device. Signals are transferred which are output as converted signals coded on the basis of a second standard into signals coded on the basis of the first standard to the reception device upon reception of signals coded on the basis of the second standard, or for transferring signals output by the logic-level conversion device upon reception of signals coded on the basis of the first standard. | ||||||
| 130 | Device for the collective processing of data | US10743274 | 2003-12-22 | US20040193667A1 | 2004-09-30 | Denis Lehongre |
| Device for processing digital data and, more particularly, for reading out the maximum or minimum value of data belonging to a set of 2n codes in which a relation of order is established and in which each of said data has a rank R comprised between 0 and 2nnull1. The device includes a conversion circuit for each digital data to be processed, which circuit generates a transform which is a binary number composed of 2nnull1 binary elements Tnullxnull with xnull1 to 2nnull1Tnull2nnull1nullTnull2nnull2null . . . Tnullxnull . . . Tnull2nullTnull1nullin which T(x)null0 when x is strictly higher than R and T(x)null1 when x is lower or equal to R. The result of the conversions is received by circuits that carry out a digital processing thereof. | ||||||
| 131 | DC free code design with state dependent mapping | US10395495 | 2003-03-24 | US20040066318A1 | 2004-04-08 | Kinhing Paul Tsang |
| A method of encoding digital information in a system is provided. The method includes receiving a sequence of user-bits and calculating a running digital sum (RDS) of the system. Also, a code word is generated based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range. In one embodiment, the sequence of user bits is 19 bits and the code word is 20 bits. | ||||||
| 132 | Method and apparatus for DC-level constrained coding | US10053885 | 2002-01-16 | US06661356B1 | 2003-12-09 | Mats Oberg |
| A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word. | ||||||
| 133 | Encoder/decoder architecture and related processing system | US09843533 | 2001-04-25 | US20020019896A1 | 2002-02-14 | William Fornaciari; Donatella Sciuto; Cristina Silvano; Roberto Zafalon; Danilo Pau |
| An encoder/decoder architecture for buses, capable of minimizing power consumption by reducing the switching activity, generates, from an input information value relating to a given instant, a corresponding current output value on encoded bus lines relating to the same given instant. The architecture including storage device for storing respective preceding values of input information and output information relating to instants preceding the aforesaid given instant. A prediction block generates, from the preceding value of input information, an estimate of the current input information value. A decorrelation block decorrelates the current input information value with respect to the said estimate. A selection block selects as the current output value one out of the current input information value, the result of the decorrelation implemented by the decorrelation block or the preceding output value. | ||||||
| 134 | Storage system employing high-rate code with constraint on run length between occurrences of an influential pattern | US08957763 | 1997-10-24 | US06246346B1 | 2001-06-12 | Robert Leslie Cloke; Patrick James Lee; Steven William McLaughlin |
| A storage system employs a method for encoding a sequence of input data blocks into a sequence of codewords. Each input data block includes a first predetermined number of bits (the data block length). Each codeword includes a second predetermined number of bits (the codeword length). The code rate, i.e., the ratio of the first number to the second number, is greater than ¾. The method is performed in a sampled-data channel in a storage system; and the channel includes a circuit the performance of which is adversely affected by an excessive run length of bits between occurrences of a predetermined influential pattern. Preferably, the influential pattern is a two-bit sequence of adjacent 1's, which favorably influences the performance of a timing recovery circuit. The method includes receiving the sequence of input data blocks and generating the sequence of codewords responsive to the received sequence of input data blocks. The sequence of codewords has a constraint on the maximum run length of bits between occurrences of the influential pattern, the maximum run length of bits being less than or equal to the codeword length. | ||||||
| 135 | Methods and apparatus for implementing run-length limited and maximum transition run codes | US09335816 | 1999-06-18 | US06241778B1 | 2001-06-05 | Adriaan J. de Lind van Wijngaarden; Emina Soljanin |
| Data words are converted to codewords in accordance with a run-length limited (RLL) or maximum transition run (MTR) code in which the codewords are subject to one or more constraints on the number of consecutive like symbols. The data words and codewords are each partitioned into a number of disjoint subsets. Associated with each of the disjoint subsets of data words is a distinct mapping. A given data word is converted to a codeword by applying to the given data word the mapping associated with the subset containing that data word. The mappings are configured to utilize symmetry whenever possible. For example, if Y=&psgr;(X) represents the mapping of a given data word X onto a corresponding codeword Y. then it is preferred that X′ and Y′ representing the words X and Y in reversed order, satisfy the relation Y′=&psgr;(X′). An example of an efficient high-rate, multi-purpose code in accordance with the invention is a rate 16/17 code satisfying (0,15,9,9) RLL and (0,3,2,2) MTR constraints. This exemplary code can be further processed using interleaving techniques to generate other higher rate codes. | ||||||
| 136 | Data processing equipment and method | US09030938 | 1998-02-26 | US06236686B1 | 2001-05-22 | Yoshiyuki Kamishima |
| Disclosed is a data processing equipment for conducting the whitener encoding to suppress DC bias in transmit data in a communication device, which has: a multiplexer which parallel-to-serial-converts transmit data and a scrambler which randomizes the converted data; a first counter which counts by +3, +1, −1 or −3 when 2-bit symbol data in the data concerned have a logical level of ‘10’, ‘11’, ‘01’ or ‘00’; a second counter which counts by +3, +1, −1 or −3 when the 2-bit symbol data in all data to be already transmitted have a logical level of ‘10’, ‘11’, ‘01’ or ‘00’; a way to compare a sign bit (MSB of counted weight value) of the first counter with a sign bit (MSB of counted weight value) the second counter; two bit-inversion circuits which invert between ‘1’ and ‘0’ of the data according to the comparison result of the comparing means; two n/2-bit shift registers which delay by n-bit data concerned; and two bit-stuff circuits which insert two-bit stuff bit to the delayed n-bit data supplied from the two n/2-bit shift registers and output the stuff-bit-inserted n-bit data to the two bit-inversion circuits. | ||||||
| 137 | Digital transmission circuit using means for introducing a redundancy on the most significant bit | US199867 | 1980-10-23 | US4369512A | 1983-01-18 | Pierre Brossard; Didier Lombard |
| Coder-decoder for a transmission channel for digital signals, said signals being constituted by a sequence of bits between a more significant bit formed by a sign bit and a less significant bit.The coder-decoder comprises on the one hand a coder constituted by a circuit able to extract the more significant bit e.g. 1 from the indicated incident digital signal, a recurrent coding circuit of ratio 2 receiving bit EB1 and supplying two redundant bits EB1a and EB1b, means for forming a coded signal having the same number of bits as the incident signal with bit EB1a as the most significant bit, the least significant bit of the incident signal being eliminated and bit EB1b being inserted between two given bits of the incident signal and on the other hand a decoder which comprises means for extracting the redundant bits EB1a and EB1b from the coded signal, a recurrent decoding circuit receiving the two bits EB1a and EB1b and supplying a sign bit EB1b, a pseudo-random bit generator and means for restoring a digital signal having the signal bits received other than EB1a and EB1b between the sign bit taken as the most significant bit and the pseudo-random bit taken as the least significant bit. | ||||||
| 138 | Digital radio communications system with high noise immunity | US67709 | 1979-08-17 | US4314371A | 1982-02-02 | Edward L. Covington; Herman D. Self |
| A digital data radio transmission system, such as may be used in communicating point-to-point by radio, in which a keyboard is used to insert a multi-decimal-digit number representing the called station. This is fed to a decimal-to-binary converter, forming a train of binary bits which are then coded in a selected manner so as to be substantially noise immune. The output of the coder then goes to the radio transmitter. At the receiving end, a similar means is provided for obtaining and storing in a 24-bit register the selected number of the called station. The output of the radio detector is then decoded to obtain the 24-bit word representing the called station, which is stored in a second register. A comparator compares the numbers stored in the two registers. When they compare positively, an alarm signal is enabled, or the receiver squelch is broken. | ||||||
| 139 | Device for transferring digital information | US899287 | 1978-04-24 | US4150404A | 1979-04-17 | Eduard J. Tercic; Nicolaas A. M. Verhoeckx |
| A data recording device having a coding device which is supplied with a sequence of information bits to be recorded. The coding device forms coded information words of at least two different lengths from the sequence of information bits. The recording device further includes a divide-by-two member connected to the output of the coding device, a scrambler connected to the output of the divide-by-two member for scrambling the output signals of the divide-by-two member; and a write head connected to the output of the scrambler for recording the scrambled output signals. | ||||||
| 140 | Biphase digital television systems | US493111 | 1974-07-30 | US3961137A | 1976-06-01 | Peter Richard Hutt; Alan Ronald Blake; Gunter VON Cavallar; Brian Neil Douglas; Philip John Dodds |
| Apparatus for processing groups of digital data for transmission comprises a run-in signal generator for providing at the output of the apparatus an output in which the groups of data are each preceded by a run-in signal, said apparatus being so constituted that the output is in the form of digital signals of the complemented type, and a start code generator operable to provide a start code with at least one break of complementation and arranged to insert a start code between each group and its preceding run-in signal.The apparatus is especially suitable for the transmission of data intermittently, e.g. during periods of a television signal unoccupied by wide-band picture signals. Because of the complementation break, the start code cannot arise from a data combination. Good reliability of reception is achieved on channels susceptible to interference.An apparatus for reception comprises a memory device controlled by a clock circuit responsive to the run-in signal, and means responsive to the start code to route the data for display purposes. | ||||||
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