Concurrent code checker and hardware efficient high- speed I/O having built- in self- test and debug features |
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| 申请号 | EP07250229.7 | 申请日 | 2007-01-19 | 公开(公告)号 | EP1814234A3 | 公开(公告)日 | 2007-08-08 |
| 申请人 | Silicon Image, Inc.; | 发明人 | Sul, Chinsong; Choi, Hoon; Ahn, Gijung; | ||||
| 摘要 | Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements. | ||||||
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| 说明书全文 | |||||||
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